<br>read 1: interrupt 'DMA done interrupt' is enabled<br>read 0: interrupt 'DMA done interrupt' is disabled
<li><b>
DMA_ERROR
</b>[<i>read-only</i>]: DMA error interrupt
<br>read 1: interrupt 'DMA error interrupt' is enabled<br>read 0: interrupt 'DMA error interrupt' is disabled
</ul>
<aname="EIC_ISR"></a>
<h3><aname="sect_3_4">3.4. Interrupt status register</a></h3>
<tablecellpadding=0cellspacing=0border=0>
<tr>
<td>
<b>HW prefix: </b>
</td>
<tdclass="td_code">
dma_eic_eic_isr
</td>
</tr>
<tr>
<td>
<b>HW address: </b>
</td>
<tdclass="td_code">
0x3
</td>
</tr>
<tr>
<td>
<b>C prefix: </b>
</td>
<tdclass="td_code">
EIC_ISR
</td>
</tr>
<tr>
<td>
<b>C offset: </b>
</td>
<tdclass="td_code">
0xc
</td>
</tr>
</table>
<p>
Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.