Add spec/ directory

6264a3ea · Tristan Gingold · e9a19175 · 6264a3ea · 6264a3ea · 6264a3ea
Commit 6264a3ea authored Jan 16, 2019 by Tristan Gingold
5 changed files
--- a/builder/spec/Manifest-syn.py
+++ b/builder/spec/Manifest-syn.py
+# HDLMake 'develop' branch required.
+#
+# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
+# branch of hdlmake, commit db4e1ab.
+
+board  = "spec"
+target = "xilinx"
+action = "synthesis"
+
+syn_device  = "xc6slx100t"
+syn_grade   = "-3"
+syn_package = "fgg484"
+syn_top     = "{name}_top"
+syn_project = "{name}.xise"
+syn_tool    = "ise"
+
+fetchto = "{fetchto}"
+
+ctrls = ["bank3_64b_32b"]
+
+syn_post_project_cmd = (
+    "$(TCL_INTERPRETER) " + \
+    fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
+    syn_tool + " $(PROJECT_FILE);" \
+    "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
+)
+
+files = [
+    "{name}.ucf",
+]
+
+modules = {{
+    "local" : [
+        "../../top/{name}",
+    ],
+}}
--- a/builder/spec/Manifest-top.py
+++ b/builder/spec/Manifest-top.py
+files = [
+    "{name}_top.vhd",
+    "../../../spec-lib/carrier_csr_wbgen2_pkg.vhd",
+    "../../../spec-lib/carrier_csr.vhd",
+    "../../../spec-lib/dma_eic.vhd",
+]
+
+fetchto = "{fetchto}"
+
+modules = {{
+    "git" : [
+        "git://ohwr.org/hdl-core-lib/general-cores.git",
+        "git://ohwr.org/hdl-core-lib/wr-cores.git",
+        "git://ohwr.org/hdl-core-lib/urv-core.git",
+        "git://ohwr.org/hdl-core-lib/mock-turtle.git",
+        "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git",
+        "git://ohwr.org/hdl-core-lib/gn4124-core.git",
+
+{modules}
+    ],
+}}
--- a/builder/spec/syn_extra_steps.tcl
+++ b/builder/spec/syn_extra_steps.tcl
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+xilinx::project save
+
+xilinx::project close
--- a/builder/spec/top.ucf
+++ b/builder/spec/top.ucf
--- a/builder/spec/top.vhd
+++ b/builder/spec/top.vhd