Adjust modules

82fd7019 · Tristan Gingold · d79a536e · 82fd7019
Commit 82fd7019 authored Feb 21, 2022 by Tristan Gingold
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Manifest.py hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py +1 -1

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--- a/hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/top/wrtd_ref_svec_tdc_fd/Manifest.py
@@ -12,7 +12,7 @@ modules = {
        "https://ohwr.org/project/vme64x-core.git",
        "https://ohwr.org/project/urv-core.git",
        "https://ohwr.org/project/mock-turtle.git",
-        "https://ohwr.org/project/fmc-tdc-1ns-5cha.git",
+        "https://ohwr.org/project/fmc-tdc.git",
        "https://ohwr.org/project/fmc-delay-1ns-8cha.git",
        "https://ohwr.org/project/ddr3-sp6-core.git",
    ],