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White Rabbit Trigger Distribution
Commit 6e4b4ef4 authored by Konstantinos Blantos's avatar Konstantinos Blantos Committed by Dimitris Lampridis
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Introduce a basic CI for simulation and synthesis

parent 71ebc42e
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Showing with 115 additions and 5 deletions
.gitlab-ci.yml 0 → 100644
View file @ 6e4b4ef4
variables:
GIT_SUBMODULE_STRATEGY: normal
GIT_DEPTH: "1"
stages:
- simulation
- build
SPEC150T-ADC simulate:
tags:
- questasim_105c
only:
- schedules
stage: simulation
script:
- /entrypoint.sh
- echo "Starting SPEC150T-ADC simulate!"
- export TMP_DIR=$(mktemp -d)
- export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
- curl $PAK | tar xJ -C $TMP_DIR
- export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
- cd hdl/testbench/wrtd_ref_spec150t_adc/
- source ~/setup_questasim.sh
- git submodule init && git submodule update
- cp /opt/compiled_libs_ise14.7/modelsim.ini .
- hdlmake makefile
- make
- vsim -c -do run.do
artifacts:
paths:
- hdl/testbench/wrtd_ref_spec150t_adc/transcript
SPEC150T-ADC build:
tags:
- ise_14.7
only:
- schedules
stage: build
script:
- /entrypoint.sh
- echo "Starting SPEC150T-ADC build!"
- export TMP_DIR=$(mktemp -d)
- export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
- curl $PAK | tar xJ -C $TMP_DIR
- export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
- cd hdl/syn/wrtd_ref_spec150t_adc/
- source ~/setup_ise147.sh
- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
- hdlmake makefile
- make
- git rev-parse HEAD | cut -c 1-8
artifacts:
name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
paths:
- hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.syr
- hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.par
- hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.twr
- hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.bit
- hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.bin
SVEC-TDC-FD simulate:
tags:
- questasim_105c
only:
- schedules
stage : simulation
script:
- /entrypoint.sh
- echo "Starting SVEC-TDC-FD simulation!"
- export TMP_DIR=$(mktemp -d)
- export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
- curl $PAK | tar xJ -C $TMP_DIR
- export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
- cd hdl/testbench/wrtd_ref_svec_tdc_fd/
- source ~/setup_questasim.sh
- cp /opt/compiled_libs_ise14.7/modelsim.ini .
- hdlmake makefile
- make
- vsim -c -do run_ci.do
artifacts:
paths:
- hdl/testbench/wrtd_ref_svec_tdc_fd/transcript
SVEC-TDC-FD build:
tags:
- ise_14.7
only:
- schedules
stage: build
script:
- /entrypoint.sh
- echo "Starting SVEC-TDC-FD build!"
- export TMP_DIR=$(mktemp -d)
- export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
- curl $PAK | tar xJ -C $TMP_DIR
- export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
- cd hdl/syn/wrtd_ref_svec_tdc_fd/
- source ~/setup_ise147.sh
- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
- hdlmake makefile
- make
- git rev-parse HEAD | cut -c 1-8
artifacts:
paths:
- hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.syr
- hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.par
- hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.twr
- hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.bit
- hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.bin
hdl/testbench/wrtd_ref_svec_tdc_fd/dut_env.sv
View file @ 6e4b4ef4
......@@ -28,6 +28,8 @@
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`timescale 1ns/1ps
module simple_tdc_driver
(
input clk,
......@@ -72,8 +74,7 @@ module simple_tdc_driver
acam_fifo_entry t;
time now;
wait (pulses.size() != 0)
;
wait (pulses.size() != 0);
t = pulses.pop_front();
now = $time;
......@@ -90,7 +91,7 @@ module simple_tdc_driver
val[27:26] = t.channel & 2'b11;
val[25:18] = start;
val[17] = 1'b1;
val[16:0] = (t.ts - start_time) / 81ps;
val[16:0] = (t.ts - start_time) / 81.0ps;
$display("[DUT] <%t> TDC: pulse at %t for channel %0d (start #0x%x, time_data 0x%x, start_time %t)",
$realtime, t.ts, t.channel, start, val[16:0], start_time);
......@@ -101,7 +102,7 @@ module simple_tdc_driver
val[27:26] = t.channel & 2'b11;
val[25:18] = start;
val[17] = 1'b0;
val[16:0] = (t.duration + t.ts - start_time) / 81ps;
val[16:0] = (t.duration + t.ts - start_time) / 81.0ps;
fifos[t.channel / 4].push_back(val);
......@@ -125,7 +126,7 @@ module simple_tdc_driver
if (restart_pulse) begin
start = 1;
restart_pulse = 0;
start01 = ($time - restart_time) / 81ps;
start01 = ($time - restart_time) / 81.0ps;
end
else begin
start_time = $time;
......
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