Initial wrtd_ref_svec_tdc_x2 design

52977ac5 · Tristan Gingold · 59677c0a · 52977ac5 · 52977ac5 · 52977ac5
Commit 52977ac5 authored Feb 16, 2021 by Tristan Gingold
5 changed files
--- a/hdl/syn/wrtd_ref_svec_tdc_x2/Manifest.py
+++ b/hdl/syn/wrtd_ref_svec_tdc_x2/Manifest.py
+board  = "svec"
+target = "xilinx"
+action = "synthesis"
+
+syn_device  = "xc6slx150t"
+syn_grade   = "-3"
+syn_package = "fgg900"
+syn_top     = "wrtd_ref_svec_tdc_x2"
+syn_project = "wrtd_ref_svec_tdc_x2.xise"
+syn_tool    = "ise"
+
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+    fetchto = "../../../dependencies"
+
+files = [
+    "wrtd_ref_svec_tdc_x2.ucf",
+    "buildinfo_pkg.vhd",
+]
+
+modules = {
+    "local" : [
+        "../../top/wrtd_ref_svec_tdc_x2",
+    ],
+}
+
+syn_pre_project_cmd = "make -C ../../../software/firmware"
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
+
+syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
+
+svec_base_ucf = ['wr', 'led', 'gpio']
+
+ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
--- a/hdl/syn/wrtd_ref_svec_tdc_x2/syn_extra_steps.tcl
+++ b/hdl/syn/wrtd_ref_svec_tdc_x2/syn_extra_steps.tcl
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+xilinx::project save
+
+xilinx::project close
--- a/hdl/syn/wrtd_ref_svec_tdc_x2/wrtd_ref_svec_tdc_x2.ucf
+++ b/hdl/syn/wrtd_ref_svec_tdc_x2/wrtd_ref_svec_tdc_x2.ucf
--- a/hdl/top/wrtd_ref_svec_tdc_x2/Manifest.py
+++ b/hdl/top/wrtd_ref_svec_tdc_x2/Manifest.py
+files = [
+    "wrtd_ref_svec_tdc_x2.vhd",
+]
+
+fetchto = "../../../dependencies"
+
+modules = {
+    "git" : [
+        "https://ohwr.org/project/svec.git",
+        "https://ohwr.org/project/general-cores.git",
+        "https://ohwr.org/project/wr-cores.git",
+        "https://ohwr.org/project/vme64x-core.git",
+        "https://ohwr.org/project/urv-core.git",
+        "https://ohwr.org/project/mock-turtle.git",
+        "https://ohwr.org/project/fmc-tdc.git",
+        "https://ohwr.org/project/fmc-delay-1ns-8cha.git",
+        "https://ohwr.org/project/ddr3-sp6-core.git",
+    ],
+}
--- a/hdl/top/wrtd_ref_svec_tdc_x2/wrtd_ref_svec_tdc_x2.vhd
+++ b/hdl/top/wrtd_ref_svec_tdc_x2/wrtd_ref_svec_tdc_x2.vhd