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White Rabbit Trigger Distribution
Commit 404aa4cf authored by Tristan Gingold's avatar Tristan Gingold
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First complete hdl generation

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builder/fmc-delay-1ns-8cha/inst.vhd 0 → 100644
View file @ 404aa4cf
-----------------------------------------------------------------------------
-- FMC FDELAY (SVEC slot #{n})
-----------------------------------------------------------------------------
cmp_fd_tdc_start{n} : IBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE)
port map (
O => fmc{n}_fd_tdc_start,
I => fmc{n}_fd_tdc_start_p_i,
IB => fmc{n}_fd_tdc_start_n_i);
U_DDR_PLL1 : entity work.fd_ddr_pll
port map (
RST => ddr1_pll_reset,
LOCKED => ddr1_pll_locked,
CLK_IN1_P => fmc{n}_fd_clk_ref_p_i,
CLK_IN1_N => fmc{n}_fd_clk_ref_n_i,
CLK_OUT1 => dcm1_clk_ref_0,
CLK_OUT2 => dcm1_clk_ref_180);
ddr1_pll_reset <= not fmc{n}_fd_pll_status_i;
fmc{n}_fd_pll_status <= fmc{n}_fd_pll_status_i and ddr1_pll_locked;
U_FineDelay_Core{n} : fine_delay_core
generic map (
g_with_wr_core => TRUE,
g_simulation => f_int2bool(g_simulation),
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_ref_0_i => dcm1_clk_ref_0,
clk_ref_180_i => dcm1_clk_ref_180,
clk_sys_i => clk_sys_62m5,
clk_dmtd_i => '0',
rst_n_i => rst_sys_62m5_n,
dcm_reset_o => open,
dcm_locked_i => ddr1_pll_locked,
trig_a_i => fmc{n}_fd_trig_a_i,
tdc_cal_pulse_o => fmc{n}_fd_tdc_cal_pulse_o,
tdc_start_i => fmc{n}_fd_tdc_start,
dmtd_fb_in_i => fmc{n}_fd_dmtd_fb_in_i,
dmtd_fb_out_i => fmc{n}_fd_dmtd_fb_out_i,
dmtd_samp_o => fmc{n}_fd_dmtd_clk_o,
led_trig_o => fmc{n}_fd_led_trig_o,
ext_rst_n_o => fmc{n}_fd_ext_rst_n_o,
pll_status_i => fmc{n}_fd_pll_status,
acam_d_o => fmc{n}_fd_tdc_data_out,
acam_d_i => fmc{n}_fd_tdc_data_in,
acam_d_oen_o => fmc{n}_fd_tdc_data_oe,
acam_emptyf_i => fmc{n}_fd_tdc_emptyf_i,
acam_alutrigger_o => fmc{n}_fd_tdc_alutrigger_o,
acam_wr_n_o => fmc{n}_fd_tdc_wr_n_o,
acam_rd_n_o => fmc{n}_fd_tdc_rd_n_o,
acam_start_dis_o => fmc{n}_fd_tdc_start_dis_o,
acam_stop_dis_o => fmc{n}_fd_tdc_stop_dis_o,
spi_cs_dac_n_o => fmc{n}_fd_spi_cs_dac_n_o,
spi_cs_pll_n_o => fmc{n}_fd_spi_cs_pll_n_o,
spi_cs_gpio_n_o => fmc{n}_fd_spi_cs_gpio_n_o,
spi_sclk_o => fmc{n}_fd_spi_sclk_o,
spi_mosi_o => fmc{n}_fd_spi_mosi_o,
spi_miso_i => fmc{n}_fd_spi_miso_i,
delay_len_o => fmc{n}_fd_delay_len_o,
delay_val_o => fmc{n}_fd_delay_val_o,
delay_pulse_o => fmc{n}_fd_delay_pulse_o,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_utc_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en({n}),
tm_clk_aux_locked_i => tm_clk_aux_locked({n}),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr({n}),
owr_en_o => fmc{n}_fd_owr_en,
owr_i => fmc{n}_fd_owr_in,
i2c_scl_oen_o => fmc{n}_fd_scl_out,
i2c_scl_i => fmc{n}_fd_scl_in,
i2c_sda_oen_o => fmc{n}_fd_sda_out,
i2c_sda_i => fmc{n}_fd_sda_in,
fmc_present_n_i => fmc{n}_prsntm2c_n_i,
wb_adr_i => fmc{n}_mux_wb_out.adr,
wb_dat_i => fmc{n}_mux_wb_out.dat,
wb_dat_o => fmc{n}_mux_wb_in.dat,
wb_sel_i => fmc{n}_mux_wb_out.sel,
wb_cyc_i => fmc{n}_mux_wb_out.cyc,
wb_stb_i => fmc{n}_mux_wb_out.stb,
wb_we_i => fmc{n}_mux_wb_out.we,
wb_ack_o => fmc{n}_mux_wb_in.ack,
wb_stall_o => fmc{n}_mux_wb_in.stall,
wb_irq_o => fmc_host_irq({n}));
cmp_fmc{n}_wb_mux : xwb_crossbar
generic map (
g_num_masters => 2,
g_num_slaves => 1,
g_registered => TRUE,
g_address => c_FMC_MUX_ADDR,
g_mask => c_FMC_MUX_MASK)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i(0) => fmc_dp_wb_out(1),
slave_i(1) => cnx_slave_in(c_WB_SLAVE_FMC{n}),
slave_o(0) => fmc_dp_wb_in(1),
slave_o(1) => cnx_slave_out(c_WB_SLAVE_FMC{n}),
master_i(0) => fmc{n}_mux_wb_in,
master_o(0) => fmc{n}_mux_wb_out);
fmc{n}_mux_wb_in.err <= '0';
fmc{n}_mux_wb_in.rty <= '0';
-- tristate buffer for the TDC data bus:
fmc{n}_fd_tdc_d_b <= fmc{n}_fd_tdc_data_out when fmc{n}_fd_tdc_data_oe = '1' else (others => 'Z');
fmc{n}_fd_tdc_oe_n_o <= '1';
fmc{n}_fd_tdc_data_in <= fmc{n}_fd_tdc_d_b;
fmc{n}_fd_onewire_b <= '0' when fmc{n}_fd_owr_en = '1' else 'Z';
fmc{n}_fd_owr_in <= fmc{n}_fd_onewire_b;
fmc{n}_scl_b <= '0' when (fmc{n}_fd_scl_out = '0') else 'Z';
fmc{n}_sda_b <= '0' when (fmc{n}_fd_sda_out = '0') else 'Z';
fmc{n}_fd_scl_in <= fmc{n}_scl_b;
fmc{n}_fd_sda_in <= fmc{n}_sda_b;
builder/fmc-delay-1ns-8cha/repo.txt 0 → 100644
View file @ 404aa4cf
git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git
builder/fmc-delay-1ns-8cha/svec-fmc1.ucf 0 → 100644
View file @ 404aa4cf
# ucfgen pin assignments for mezzanine fmc-delay-v4 slot 1
NET "fmc1_fd_clk_ref_p_i" LOC = "AH16";
NET "fmc1_fd_clk_ref_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_clk_ref_n_i" LOC = "AK16";
NET "fmc1_fd_clk_ref_n_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_tdc_start_p_i" LOC = "AF16";
NET "fmc1_fd_tdc_start_p_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_tdc_start_n_i" LOC = "AG16";
NET "fmc1_fd_tdc_start_n_i" IOSTANDARD = "LVDS_25";
NET "fmc1_fd_delay_len_o[3]" LOC = "AB21";
NET "fmc1_fd_delay_len_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[3]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[3]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[2]" LOC = "AC21";
NET "fmc1_fd_delay_len_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[1]" LOC = "AD24";
NET "fmc1_fd_delay_len_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[1]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[1]" DRIVE = 4;
NET "fmc1_fd_delay_len_o[0]" LOC = "AC24";
NET "fmc1_fd_delay_len_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_len_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_len_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_pulse_o[3]" LOC = "AE22";
NET "fmc1_fd_delay_pulse_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[1]" LOC = "AD17";
NET "fmc1_fd_delay_pulse_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[2]" LOC = "AD22";
NET "fmc1_fd_delay_pulse_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_pulse_o[0]" LOC = "AB17";
NET "fmc1_fd_delay_pulse_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[3]" LOC = "AA19";
NET "fmc1_fd_delay_val_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[3]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[3]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[1]" LOC = "W19";
NET "fmc1_fd_delay_val_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[1]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[1]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[7]" LOC = "Y21";
NET "fmc1_fd_delay_val_o[7]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[7]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[7]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[5]" LOC = "W20";
NET "fmc1_fd_delay_val_o[5]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[5]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[5]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[9]" LOC = "AA22";
NET "fmc1_fd_delay_val_o[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[9]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[9]" DRIVE = 4;
NET "fmc1_fd_spi_mosi_o" LOC = "AB20";
NET "fmc1_fd_spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_sclk_o" LOC = "AC19";
NET "fmc1_fd_spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_oe_n_o" LOC = "AF25";
NET "fmc1_fd_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_start_dis_o" LOC = "AE24";
NET "fmc1_fd_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_gpio_n_o" LOC = "AE19";
NET "fmc1_fd_spi_cs_gpio_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_cal_pulse_o" LOC = "AE23";
NET "fmc1_fd_tdc_cal_pulse_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_clk_o" LOC = "AE21";
NET "fmc1_fd_dmtd_clk_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_wr_n_o" LOC = "AC16";
NET "fmc1_fd_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_alutrigger_o" LOC = "AB14";
NET "fmc1_fd_tdc_alutrigger_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_led_trig_o" LOC = "Y17";
NET "fmc1_fd_led_trig_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[26]" LOC = "Y15";
NET "fmc1_fd_tdc_d_b[26]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[24]" LOC = "AC15";
NET "fmc1_fd_tdc_d_b[24]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[20]" LOC = "AE15";
NET "fmc1_fd_tdc_d_b[20]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[22]" LOC = "Y16";
NET "fmc1_fd_tdc_d_b[22]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[18]" LOC = "Y14";
NET "fmc1_fd_tdc_d_b[18]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[16]" LOC = "W14";
NET "fmc1_fd_tdc_d_b[16]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[10]" LOC = "AB12";
NET "fmc1_fd_tdc_d_b[10]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[14]" LOC = "AD12";
NET "fmc1_fd_tdc_d_b[14]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[8]" LOC = "AD10";
NET "fmc1_fd_tdc_d_b[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[12]" LOC = "AE11";
NET "fmc1_fd_tdc_d_b[12]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[3]" LOC = "AJ15";
NET "fmc1_fd_tdc_d_b[3]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[5]" LOC = "AE13";
NET "fmc1_fd_tdc_d_b[5]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[7]" LOC = "AC11";
NET "fmc1_fd_tdc_d_b[7]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[2]" LOC = "AG8";
NET "fmc1_fd_tdc_d_b[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_trig_a_i" LOC = "AJ17";
NET "fmc1_fd_trig_a_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" LOC = "AB19";
NET "fmc1_fd_delay_val_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[2]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[2]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[0]" LOC = "Y19";
NET "fmc1_fd_delay_val_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[0]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[0]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[6]" LOC = "AA21";
NET "fmc1_fd_delay_val_o[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[6]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[6]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[4]" LOC = "Y20";
NET "fmc1_fd_delay_val_o[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[4]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[4]" DRIVE = 4;
NET "fmc1_fd_delay_val_o[8]" LOC = "AC22";
NET "fmc1_fd_delay_val_o[8]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_delay_val_o[8]" SLEW = SLOW;
NET "fmc1_fd_delay_val_o[8]" DRIVE = 4;
NET "fmc1_fd_spi_miso_i" LOC = "AC20";
NET "fmc1_fd_spi_miso_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_pll_n_o" LOC = "AD19";
NET "fmc1_fd_spi_cs_pll_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_spi_cs_dac_n_o" LOC = "AG25";
NET "fmc1_fd_spi_cs_dac_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_stop_dis_o" LOC = "AF24";
NET "fmc1_fd_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_ext_rst_n_o" LOC = "AF19";
NET "fmc1_fd_ext_rst_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_pll_status_i" LOC = "AF23";
NET "fmc1_fd_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_out_i" LOC = "AF21";
NET "fmc1_fd_dmtd_fb_out_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_rd_n_o" LOC = "AD16";
NET "fmc1_fd_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_emptyf_i" LOC = "AC14";
NET "fmc1_fd_tdc_emptyf_i" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_onewire_b" LOC = "AA17";
NET "fmc1_fd_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[27]" LOC = "AA15";
NET "fmc1_fd_tdc_d_b[27]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[25]" LOC = "AD15";
NET "fmc1_fd_tdc_d_b[25]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[21]" LOC = "AF15";
NET "fmc1_fd_tdc_d_b[21]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[23]" LOC = "AB16";
NET "fmc1_fd_tdc_d_b[23]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[19]" LOC = "AA14";
NET "fmc1_fd_tdc_d_b[19]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[17]" LOC = "Y13";
NET "fmc1_fd_tdc_d_b[17]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[11]" LOC = "AC12";
NET "fmc1_fd_tdc_d_b[11]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[15]" LOC = "AE12";
NET "fmc1_fd_tdc_d_b[15]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[9]" LOC = "AE10";
NET "fmc1_fd_tdc_d_b[9]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[13]" LOC = "AF11";
NET "fmc1_fd_tdc_d_b[13]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[1]" LOC = "AK15";
NET "fmc1_fd_tdc_d_b[1]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[4]" LOC = "AF13";
NET "fmc1_fd_tdc_d_b[4]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[6]" LOC = "AD11";
NET "fmc1_fd_tdc_d_b[6]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_tdc_d_b[0]" LOC = "AH8";
NET "fmc1_fd_tdc_d_b[0]" IOSTANDARD = "LVCMOS25";
NET "fmc1_fd_dmtd_fb_in_i" LOC = "AK17";
NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
builder/fmc-delay-1ns-8cha/top.vhd 0 → 100644
View file @ 404aa4cf
---------------------------------------------------------------------------
-- FMC slot {n} pins (FDELAY mezzanine)
---------------------------------------------------------------------------
fmc{n}_fd_tdc_start_p_i : in std_logic;
fmc{n}_fd_tdc_start_n_i : in std_logic;
fmc{n}_fd_clk_ref_p_i : in std_logic;
fmc{n}_fd_clk_ref_n_i : in std_logic;
fmc{n}_fd_trig_a_i : in std_logic;
fmc{n}_fd_tdc_cal_pulse_o : out std_logic;
fmc{n}_fd_tdc_d_b : inout std_logic_vector(27 downto 0);
fmc{n}_fd_tdc_emptyf_i : in std_logic;
fmc{n}_fd_tdc_alutrigger_o : out std_logic;
fmc{n}_fd_tdc_wr_n_o : out std_logic;
fmc{n}_fd_tdc_rd_n_o : out std_logic;
fmc{n}_fd_tdc_oe_n_o : out std_logic;
fmc{n}_fd_led_trig_o : out std_logic;
fmc{n}_fd_tdc_start_dis_o : out std_logic;
fmc{n}_fd_tdc_stop_dis_o : out std_logic;
fmc{n}_fd_spi_cs_dac_n_o : out std_logic;
fmc{n}_fd_spi_cs_pll_n_o : out std_logic;
fmc{n}_fd_spi_cs_gpio_n_o : out std_logic;
fmc{n}_fd_spi_sclk_o : out std_logic;
fmc{n}_fd_spi_mosi_o : out std_logic;
fmc{n}_fd_spi_miso_i : in std_logic;
fmc{n}_fd_delay_len_o : out std_logic_vector(3 downto 0);
fmc{n}_fd_delay_val_o : out std_logic_vector(9 downto 0);
fmc{n}_fd_delay_pulse_o : out std_logic_vector(3 downto 0);
fmc{n}_fd_dmtd_clk_o : out std_logic;
fmc{n}_fd_dmtd_fb_in_i : in std_logic;
fmc{n}_fd_dmtd_fb_out_i : in std_logic;
fmc{n}_fd_pll_status_i : in std_logic;
fmc{n}_fd_ext_rst_n_o : out std_logic;
fmc{n}_fd_onewire_b : inout std_logic;
builder/fmc-tdc-1ns-5cha/inst.vhd 0 → 100644
View file @ 404aa4cf
-----------------------------------------------------------------------------
-- FMC TDC (SVEC slot #{n})
-----------------------------------------------------------------------------
U_TDC_Core : fmc_tdc_wrapper
generic map (
g_simulation => f_int2bool(g_simulation),
g_with_direct_readout => TRUE)
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n,
pll_sclk_o => fmc{n}_tdc_pll_sclk_o,
pll_sdi_o => fmc{n}_tdc_pll_sdi_o,
pll_cs_o => fmc{n}_tdc_pll_cs_n_o,
pll_dac_sync_o => fmc{n}_tdc_pll_dac_sync_n_o,
pll_sdo_i => fmc{n}_tdc_pll_sdo_i,
pll_status_i => fmc{n}_tdc_pll_status_i,
tdc_clk_125m_p_i => fmc{n}_tdc_125m_clk_p_i,
tdc_clk_125m_n_i => fmc{n}_tdc_125m_clk_n_i,
acam_refclk_p_i => fmc{n}_tdc_acam_refclk_p_i,
acam_refclk_n_i => fmc{n}_tdc_acam_refclk_n_i,
start_from_fpga_o => fmc{n}_tdc_start_from_fpga_o,
err_flag_i => fmc{n}_tdc_err_flag_i,
int_flag_i => fmc{n}_tdc_int_flag_i,
start_dis_o => fmc{n}_tdc_start_dis_o,
stop_dis_o => fmc{n}_tdc_stop_dis_o,
data_bus_io => fmc{n}_tdc_data_bus_io,
address_o => fmc{n}_tdc_address_o,
cs_n_o => fmc{n}_tdc_cs_n_o,
oe_n_o => fmc{n}_tdc_oe_n_o,
rd_n_o => fmc{n}_tdc_rd_n_o,
wr_n_o => fmc{n}_tdc_wr_n_o,
ef1_i => fmc{n}_tdc_ef1_i,
ef2_i => fmc{n}_tdc_ef2_i,
enable_inputs_o => fmc{n}_tdc_enable_inputs_o,
term_en_1_o => fmc{n}_tdc_term_en_1_o,
term_en_2_o => fmc{n}_tdc_term_en_2_o,
term_en_3_o => fmc{n}_tdc_term_en_3_o,
term_en_4_o => fmc{n}_tdc_term_en_4_o,
term_en_5_o => fmc{n}_tdc_term_en_5_o,
tdc_led_status_o => fmc{n}_tdc_led_status_o,
tdc_led_trig1_o => fmc{n}_tdc_led_trig1_o,
tdc_led_trig2_o => fmc{n}_tdc_led_trig2_o,
tdc_led_trig3_o => fmc{n}_tdc_led_trig3_o,
tdc_led_trig4_o => fmc{n}_tdc_led_trig4_o,
tdc_led_trig5_o => fmc{n}_tdc_led_trig5_o,
tdc_in_fpga_1_i => fmc{n}_tdc_in_fpga_1_i,
tdc_in_fpga_2_i => fmc{n}_tdc_in_fpga_2_i,
tdc_in_fpga_3_i => fmc{n}_tdc_in_fpga_3_i,
tdc_in_fpga_4_i => fmc{n}_tdc_in_fpga_4_i,
tdc_in_fpga_5_i => fmc{n}_tdc_in_fpga_5_i,
mezz_scl_i => fmc{n}_scl_b,
mezz_sda_i => fmc{n}_sda_b,
mezz_scl_o => fmc{n}_scl_out,
mezz_sda_o => fmc{n}_sda_out,
mezz_one_wire_b => fmc{n}_tdc_one_wire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_tai,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
tm_clk_aux_locked_i => tm_clk_aux_locked(0),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr(0),
direct_slave_i => fmc_dp_wb_out(0),
direct_slave_o => fmc_dp_wb_in(0),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC{n}),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC{n}),
irq_o => fmc_host_irq({n}),
clk_125m_tdc_o => tdc_clk_125m);
fmc{n}_scl_b <= '0' when fmc{n}_scl_out = '0' else 'Z';
fmc{n}_sda_b <= '0' when fmc{n}_sda_out = '0' else 'Z';
builder/fmc-tdc-1ns-5cha/repo.txt 0 → 100644
View file @ 404aa4cf
git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git
builder/fmc-tdc-1ns-5cha/svec-fmc0.ucf 0 → 100644
View file @ 404aa4cf
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "fmc0_tdc_acam_refclk_p_i" LOC = "H15";
NET "fmc0_tdc_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_acam_refclk_n_i" LOC = "G15";
NET "fmc0_tdc_acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_125m_clk_p_i" LOC = "E16";
NET "fmc0_tdc_125m_clk_p_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_125m_clk_n_i" LOC = "D16";
NET "fmc0_tdc_125m_clk_n_i" IOSTANDARD = "LVDS_25";
NET "fmc0_tdc_led_trig1_o" LOC = "H13";
NET "fmc0_tdc_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig2_o" LOC = "H11";
NET "fmc0_tdc_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig3_o" LOC = "G11";
NET "fmc0_tdc_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_1_o" LOC = "C16";
NET "fmc0_tdc_term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_2_o" LOC = "A16";
NET "fmc0_tdc_term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_ef1_i" LOC = "F19";
NET "fmc0_tdc_ef1_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_ef2_i" LOC = "E19";
NET "fmc0_tdc_ef2_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_3_o" LOC = "F15";
NET "fmc0_tdc_term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_4_o" LOC = "E15";
NET "fmc0_tdc_term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_term_en_5_o" LOC = "F13";
NET "fmc0_tdc_term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_status_o" LOC = "E13";
NET "fmc0_tdc_led_status_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig4_o" LOC = "L11";
NET "fmc0_tdc_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_led_trig5_o" LOC = "K11";
NET "fmc0_tdc_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sclk_o" LOC = "M15";
NET "fmc0_tdc_pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_dac_sync_n_o" LOC = "K15";
NET "fmc0_tdc_pll_dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_cs_n_o" LOC = "L14";
NET "fmc0_tdc_pll_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_cs_n_o" LOC = "K14";
NET "fmc0_tdc_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_err_flag_i" LOC = "H16";
NET "fmc0_tdc_err_flag_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_int_flag_i" LOC = "G16";
NET "fmc0_tdc_int_flag_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_dis_o" LOC = "F11";
NET "fmc0_tdc_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_stop_dis_o" LOC = "E11";
NET "fmc0_tdc_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sdo_i" LOC = "L13";
NET "fmc0_tdc_pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_status_i" LOC = "E9";
NET "fmc0_tdc_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_pll_sdi_o" LOC = "M13";
NET "fmc0_tdc_pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_from_fpga_o" LOC = "F9";
NET "fmc0_tdc_start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_start_from_fpga_o" SLEW = SLOW;
NET "fmc0_tdc_start_from_fpga_o" DRIVE = 4;
NET "fmc0_tdc_data_bus_io[27]" LOC = "E17";
NET "fmc0_tdc_data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[26]" LOC = "F17";
NET "fmc0_tdc_data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[25]" LOC = "F18";
NET "fmc0_tdc_data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[24]" LOC = "G18";
NET "fmc0_tdc_data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[23]" LOC = "F20";
NET "fmc0_tdc_data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[22]" LOC = "G20";
NET "fmc0_tdc_data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[21]" LOC = "E21";
NET "fmc0_tdc_data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[20]" LOC = "F21";
NET "fmc0_tdc_data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[19]" LOC = "K21";
NET "fmc0_tdc_data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[18]" LOC = "L21";
NET "fmc0_tdc_data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[17]" LOC = "L20";
NET "fmc0_tdc_data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[16]" LOC = "M20";
NET "fmc0_tdc_data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[15]" LOC = "F22";
NET "fmc0_tdc_data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[14]" LOC = "G22";
NET "fmc0_tdc_data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[13]" LOC = "L19";
NET "fmc0_tdc_data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[12]" LOC = "M19";
NET "fmc0_tdc_data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[11]" LOC = "E23";
NET "fmc0_tdc_data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[10]" LOC = "F23";
NET "fmc0_tdc_data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[9]" LOC = "A25";
NET "fmc0_tdc_data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[8]" LOC = "B25";
NET "fmc0_tdc_data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[7]" LOC = "G21";
NET "fmc0_tdc_data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[6]" LOC = "C24";
NET "fmc0_tdc_data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[5]" LOC = "H21";
NET "fmc0_tdc_data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[4]" LOC = "D24";
NET "fmc0_tdc_data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[3]" LOC = "D25";
NET "fmc0_tdc_data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[2]" LOC = "E25";
NET "fmc0_tdc_data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[1]" LOC = "H22";
NET "fmc0_tdc_data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_data_bus_io[0]" LOC = "J22";
NET "fmc0_tdc_data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[3]" LOC = "F14";
NET "fmc0_tdc_address_o[3]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[2]" LOC = "G14";
NET "fmc0_tdc_address_o[2]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[1]" LOC = "H14";
NET "fmc0_tdc_address_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_address_o[0]" LOC = "J14";
NET "fmc0_tdc_address_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_oe_n_o" LOC = "G12";
NET "fmc0_tdc_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_oe_n_o" SLEW = SLOW;
NET "fmc0_tdc_oe_n_o" DRIVE = 4;
NET "fmc0_tdc_rd_n_o" LOC = "A15";
NET "fmc0_tdc_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_rd_n_o" SLEW = SLOW;
NET "fmc0_tdc_rd_n_o" DRIVE = 4;
NET "fmc0_tdc_wr_n_o" LOC = "B15";
NET "fmc0_tdc_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_wr_n_o" SLEW = SLOW;
NET "fmc0_tdc_wr_n_o" DRIVE = 4;
NET "fmc0_tdc_enable_inputs_o" LOC = "J12";
NET "fmc0_tdc_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "fmc0_tdc_one_wire_b" LOC = "H12";
NET "fmc0_tdc_one_wire_b" IOSTANDARD = "LVCMOS25";
builder/fmc-tdc-1ns-5cha/top.vhd 0 → 100644
View file @ 404aa4cf
---------------------------------------------------------------------------
-- FMC slot {n} pins (TDC mezzanine)
---------------------------------------------------------------------------
-- TDC1 PLL AD9516 and DAC AD5662 interface
fmc{n}_tdc_pll_sclk_o : out std_logic;
fmc{n}_tdc_pll_sdi_o : out std_logic;
fmc{n}_tdc_pll_cs_n_o : out std_logic;
fmc{n}_tdc_pll_dac_sync_n_o : out std_logic;
fmc{n}_tdc_pll_sdo_i : in std_logic;
fmc{n}_tdc_pll_status_i : in std_logic;
fmc{n}_tdc_125m_clk_p_i : in std_logic;
fmc{n}_tdc_125m_clk_n_i : in std_logic;
fmc{n}_tdc_acam_refclk_p_i : in std_logic;
fmc{n}_tdc_acam_refclk_n_i : in std_logic;
-- TDC1 ACAM timing interface
fmc{n}_tdc_start_from_fpga_o : out std_logic;
fmc{n}_tdc_err_flag_i : in std_logic;
fmc{n}_tdc_int_flag_i : in std_logic;
fmc{n}_tdc_start_dis_o : out std_logic;
fmc{n}_tdc_stop_dis_o : out std_logic;
-- TDC1 ACAM data interface
fmc{n}_tdc_data_bus_io : inout std_logic_vector(27 downto 0);
fmc{n}_tdc_address_o : out std_logic_vector(3 downto 0);
fmc{n}_tdc_cs_n_o : out std_logic;
fmc{n}_tdc_oe_n_o : out std_logic;
fmc{n}_tdc_rd_n_o : out std_logic;
fmc{n}_tdc_wr_n_o : out std_logic;
fmc{n}_tdc_ef1_i : in std_logic;
fmc{n}_tdc_ef2_i : in std_logic;
-- TDC1 Input Logic
fmc{n}_tdc_enable_inputs_o : out std_logic;
fmc{n}_tdc_term_en_1_o : out std_logic;
fmc{n}_tdc_term_en_2_o : out std_logic;
fmc{n}_tdc_term_en_3_o : out std_logic;
fmc{n}_tdc_term_en_4_o : out std_logic;
fmc{n}_tdc_term_en_5_o : out std_logic;
-- TDC1 1-wire UniqueID & Thermometer
fmc{n}_tdc_one_wire_b : inout std_logic;
-- TDC1 EEPROM I2C
fmc{n}_tdc_scl_b : inout std_logic;
fmc{n}_tdc_sda_b : inout std_logic;
-- TDC1 LEDs
fmc{n}_tdc_led_status_o : out std_logic;
fmc{n}_tdc_led_trig1_o : out std_logic;
fmc{n}_tdc_led_trig2_o : out std_logic;
fmc{n}_tdc_led_trig3_o : out std_logic;
fmc{n}_tdc_led_trig4_o : out std_logic;
fmc{n}_tdc_led_trig5_o : out std_logic;
-- TDC1 Input channels
-- also arriving to the FPGA (not used for the moment)
fmc{n}_tdc_in_fpga_1_i : in std_logic;
fmc{n}_tdc_in_fpga_2_i : in std_logic;
fmc{n}_tdc_in_fpga_3_i : in std_logic;
fmc{n}_tdc_in_fpga_4_i : in std_logic;
fmc{n}_tdc_in_fpga_5_i : in std_logic;
builder/svec/Manifest-syn.py 0 → 100644
View file @ 404aa4cf
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "{name}_top"
syn_project = "{name}.xise"
syn_tool = "ise"
fetchto = "{fetchto}"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files = [
"{name}.ucf",
]
modules = {{
"local" : [
"../../top/{name}",
],
}}
builder/svec/Manifest-top.py 0 → 100644
View file @ 404aa4cf
files = [
"{name}_top.vhd",
]
fetchto = "{fetchto}"
modules = {{
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/mock-turtle.git",
{modules}
],
}}
builder/svec/syn_extra_steps.tcl 0 → 100644
View file @ 404aa4cf
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project save
xilinx::project close
builder/svec/top.ucf 0 → 100644
View file @ 404aa4cf
This diff is collapsed.
builder/svec/top.vhd 0 → 100644
View file @ 404aa4cf
This diff is collapsed.
builder/wrtd_builder.py
View file @ 404aa4cf
import yaml
import argparse
import sys
import os.path
import glob
import shutil
data_dir = None
def error(msg):
sys.stderr.write(msg + '\n')
sys.exit(1)
class Result(object):
def __init__(self):
self.top_template = None
self.mt_config = None
def parse(filename):
d = yaml.load(open(filename))
if 'wrtd-board' not in d:
......@@ -74,14 +85,133 @@ def build_mt_config(desc):
return res
def board_svec(res, desc, slots):
if len(slots) > 2:
error('SVEC can have only 2 slots')
for k in slots.keys():
if k not in [0, 1]:
error('incorrect slot id {} for SVEC'.format(k))
boards = { 'svec': board_svec }
def maybe_mkdir(path):
try:
os.mkdir(path)
except FileExistsError:
pass
def compute_fetchto(relfile):
fetchto_dir = os.path.join(data_dir, "..", "dependencies")
if os.path.isabs(data_dir):
return os.path.normpath(fetchto_dir)
else:
return os.path.relpath(fetchto_dir, os.path.dirname(relfile))
def generate_hdl(res, board, slots):
# Build ports
ports = ""
for k, v in slots.items():
tmpl = open(os.path.join(data_dir, v, 'top.vhd')).read()
ports += tmpl.format(n=k)
ports += '\n'
res.ports = ports
# Build instances
insts = ""
for k, v in slots.items():
tmpl = open(os.path.join(data_dir, v, 'inst.vhd')).read()
insts += tmpl.format(n=k)
insts += '\n'
res.instances = insts
# Top vhdl file
maybe_mkdir("hdl")
maybe_mkdir(os.path.join("hdl", "top"))
maybe_mkdir(os.path.join("hdl", "top", res.name))
top_filename = os.path.join("hdl", "top", res.name,
"{}_top.vhd".format(res.name))
print("Writing {}".format(top_filename))
top_template = open(os.path.join(data_dir, board, 'top.vhd')).read()
top = open(top_filename, "w")
top.write(top_template.format(name=res.name,
ports=res.ports,
mt_config=res.mt_config,
instances=res.instances))
top.close()
# Top Manifest
manifest_filename = os.path.join("hdl", "top", res.name, "Manifest.py")
manifest_template = open(
os.path.join(data_dir, board, 'Manifest-top.py')).read()
modules_set = {v for v in slots.values()}
modules = ""
for m in modules_set:
repo = open(os.path.join(data_dir, m, 'repo.txt')).read().rstrip()
modules += ' "{}",\n'.format(repo)
print("Writing {}".format(manifest_filename))
manifest = open(manifest_filename, "w")
dependencies = compute_fetchto(manifest_filename)
manifest.write(manifest_template.format(name=res.name, modules=modules,
fetchto=dependencies))
manifest.close()
# syn Manifest
maybe_mkdir(os.path.join("hdl", "syn"))
maybe_mkdir(os.path.join("hdl", "syn", res.name))
manifest_filename = os.path.join("hdl", "syn", res.name, "Manifest.py")
manifest_template = open(
os.path.join(data_dir, board, 'Manifest-syn.py')).read()
print("Writing {}".format(manifest_filename))
manifest = open(manifest_filename, "w")
dependencies = compute_fetchto(manifest_filename)
manifest.write(manifest_template.format(name=res.name,
fetchto=dependencies))
manifest.close()
# ucf
ucf_filename = os.path.join("hdl", "syn", res.name, res.name + ".ucf")
ucf_template = open(os.path.join(data_dir, board, "top.ucf")).read()
for k, v in slots.items():
fmc_filename = os.path.join(
data_dir, v, "{}-fmc{}.ucf".format(board, k))
ucf_fmc = open(fmc_filename).read()
ucf_template += ucf_fmc
print("Writing {}".format(ucf_filename))
ucf = open(ucf_filename, "w")
ucf.write(ucf_template)
ucf.close()
# Copy tcl files
for f in glob.glob(os.path.join(data_dir, board, "*.tcl")):
print("Writing {}".format(os.path.basename(f)))
shutil.copy(f, os.path.join("hdl", "syn", res.name))
def main():
global data_dir
aparser = argparse.ArgumentParser(description='wrtd config generator')
aparser.add_argument('filename', help='YAML description file')
args = aparser.parse_args()
data_dir = os.path.dirname(__file__)
res = Result()
desc = parse(args.filename)
mt_config = build_mt_config(desc)
print(mt_config)
res.name = desc['name']
res.mt_config = build_mt_config(desc)
slots = desc['slots']
board = desc['board']
if board not in boards:
error('unknown board "{}"'.format(board))
boards[board](res, desc, slots)
generate_hdl(res, board, slots)
if __name__ == '__main__':
main()
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