fmc-adc: adjust constraints, adjust VIC vector.

27a338fc · Tristan Gingold · 2a34d662 · 27a338fc · 27a338fc
Commit 27a338fc authored Dec 10, 2018 by Tristan Gingold
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svec-fmc0.ucf builder/fmc-adc-100m14b4cha/svec-fmc0.ucf +1 -1

top.vhd builder/svec/top.vhd +2 -2

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--- a/builder/fmc-adc-100m14b4cha/svec-fmc0.ucf
+++ b/builder/fmc-adc-100m14b4cha/svec-fmc0.ucf
@@ -191,7 +191,7 @@ NET "cmp_ddr0_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;

 # Ignore async reset to DDR controller
 NET "rst_ddr_333m_n" TPTHRU = ddr0_rst;
-#ERR TIMESPEC TS_ddr0_rst_tig = FROM FFS THRU ddr0_rst TIG;
+TIMESPEC TS_ddr0_rst_tig = FROM FFS THRU ddr0_rst TIG;

 #----------------------------------------
 # Cross-clock domain sync

--- a/builder/svec/top.vhd
+++ b/builder/svec/top.vhd
@@ -246,7 +246,7 @@ architecture arch of {name}_top is

  -- not really used, will be reprogrammed by software
  constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 5) := (
-    0 => x"00013000",   -- FMC0
+    0 => x"00011500",   -- FMC0  EIC address
    1 => x"00018000",   -- FMC1
    2 => x"00020000",   -- MT Mqueue in interrupt
    3 => x"00020001",   -- MT Mqueue out interrupt
@@ -292,7 +292,7 @@ architecture arch of {name}_top is
  attribute keep of fmc0_clk_125m  : signal is "TRUE";
  attribute keep of fmc1_clk_125m  : signal is "TRUE";
  attribute keep of rst_ddr_333m_n : signal is "TRUE";
-  
+
  -- I2C EEPROM
  signal eeprom_sda_in  : std_logic;
  signal eeprom_sda_out : std_logic;