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White Rabbit Trigger Distribution
Commit 1feeb781 authored by Tristan Gingold's avatar Tristan Gingold
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tdc_x2: add cheby generated map

parent a06106d6
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hdl/top/wrtd_ref_svec_tdc_x2/Manifest.py
View file @ 1feeb781
files = [
"wrtd_ref_svec_tdc_x2.vhd",
"wrtd_tdc_x2_host_map.vhd",
]
fetchto = "../../../dependencies"
......
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_ref_svec_tdc_x2.vhd
View file @ 1feeb781
......@@ -304,51 +304,11 @@ entity wrtd_ref_svec_tdc_x2 is
end entity wrtd_ref_svec_tdc_x2;
architecture arch of wrtd_ref_svec_tdc_x2 is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- WRTD Node identification (WTN2)
constant c_WRTD_NODE_ID : std_logic_vector(31 downto 0) := x"5754_4E02";
-- Number of masters attached to the primary wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 4;
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_VME : integer := 0;
-- Primary Wishbone slave(s) offsets
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FDL : integer := 1;
constant c_WB_SLAVE_TDC : integer := 2;
constant c_WB_SLAVE_MT : integer := 3;
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FDL => x"0000_8000",
c_WB_SLAVE_TDC => x"0001_0000",
c_WB_SLAVE_MT => x"0002_0000");
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes
c_WB_SLAVE_FDL => x"0003_f800", -- 0x800 bytes
c_WB_SLAVE_TDC => x"0003_0000", -- 0x10000 bytes
c_WB_SLAVE_MT => x"0002_0000"); -- 0x20000 bytes
constant c_FMC_MUX_ADDR : t_wishbone_address_array(0 downto 0) :=
(0 => x"00000000");
constant c_FMC_MUX_MASK : t_wishbone_address_array(0 downto 0) :=
(0 => x"10000000");
constant c_METADATA_ADDR : t_wishbone_address := x"0000_4000";
constant c_MT_CONFIG : t_mt_config :=
(
......@@ -386,13 +346,17 @@ architecture arch of wrtd_ref_svec_tdc_x2 is
-- Signals
-----------------------------------------------------------------------------
-- Wishbone buse(s) from masters attached to crossbar
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal master_wb_out : t_wishbone_master_out;
signal master_wb_in : t_wishbone_master_in;
-- Wishbone buse(s) to slaves attached to crossbar
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal metadata_wb_out : t_wishbone_slave_out;
signal metadata_wb_in : t_wishbone_slave_in;
signal tdc0_wb_out : t_wishbone_slave_out;
signal tdc0_wb_in : t_wishbone_slave_in;
signal tdc1_wb_out : t_wishbone_slave_out;
signal tdc1_wb_in : t_wishbone_slave_in;
signal mt_wb_out : t_wishbone_slave_out;
signal mt_wb_in : t_wishbone_slave_in;
-- clock and reset
signal areset_n : std_logic;
......@@ -473,8 +437,8 @@ begin -- architecture arch
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
wb_i => metadata_wb_in,
wb_o => metadata_wb_out);
inst_svec_base : entity work.svec_base_wr
generic map (
......@@ -582,28 +546,27 @@ begin -- architecture arch
link_ok_o => open,
led_link_o => wr_led_link,
led_act_o => wr_led_act,
app_wb_o => cnx_master_out(c_WB_MASTER_VME),
app_wb_i => cnx_master_in(c_WB_MASTER_VME));
app_wb_o => master_wb_out,
app_wb_i => master_wb_in);
-----------------------------------------------------------------------------
-- Primary wishbone Crossbar
-----------------------------------------------------------------------------
cmp_sdb_crossbar : xwb_crossbar
generic map (
g_VERBOSE => FALSE,
g_NUM_MASTERS => c_NUM_WB_MASTERS,
g_NUM_SLAVES => c_NUM_WB_SLAVES,
g_REGISTERED => TRUE,
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
inst_host_memmap: entity work.wrtd_tdc_x2_host_map
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => master_wb_out,
wb_o => master_wb_in,
metadata_i => metadata_wb_out,
metadata_o => metadata_wb_in,
tdc0_i => tdc0_wb_out,
tdc0_o => tdc0_wb_in,
tdc1_i => tdc1_wb_out,
tdc1_o => tdc1_wb_in,
mt_i => mt_wb_out,
mt_o => mt_wb_in);
cmp_vme_led_extend : gc_extend_pulse
generic map (
......@@ -611,7 +574,7 @@ begin -- architecture arch
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_WB_MASTER_VME).cyc,
pulse_i => master_wb_out.cyc,
extended_o => vme_access_led);
-----------------------------------------------------------------------------
......@@ -633,8 +596,8 @@ begin -- architecture arch
dp_master_i => fmc_dp_wb_in,
rmq_endpoint_o => rmq_endpoint_out,
rmq_endpoint_i => rmq_endpoint_in,
host_slave_i => cnx_slave_in(c_WB_SLAVE_MT),
host_slave_o => cnx_slave_out(c_WB_SLAVE_MT),
host_slave_i => mt_wb_in,
host_slave_o => mt_wb_out,
clk_ref_i => clk_ref_125m,
tm_i => tm,
hmq_in_irq_o => irq_vector(2),
......@@ -753,8 +716,8 @@ begin -- architecture arch
tm_dac_wr_i => tm_dac_wr(0),
direct_slave_i => fmc_dp_wb_out(0),
direct_slave_o => fmc_dp_wb_in(0),
slave_i => cnx_slave_in(c_WB_SLAVE_TDC),
slave_o => cnx_slave_out(c_WB_SLAVE_TDC),
slave_i => tdc0_wb_in,
slave_o => tdc0_wb_out,
irq_o => irq_vector(0),
clk_125m_tdc_o => tdc_clk_125m);
......@@ -825,8 +788,8 @@ begin -- architecture arch
tm_dac_wr_i => tm_dac_wr(0),
direct_slave_i => fmc_dp_wb_out(1),
direct_slave_o => fmc_dp_wb_in(1),
slave_i => cnx_slave_in(c_WB_SLAVE_TDC),
slave_o => cnx_slave_out(c_WB_SLAVE_TDC),
slave_i => tdc1_wb_in,
slave_o => tdc1_wb_out,
irq_o => irq_vector(1),
clk_125m_tdc_o => tdc_clk_125m);
......
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_tdc_x2_host_map.cheby 0 → 100644
View file @ 1feeb781
memory-map:
name: wrtd_tdc_x2_host_map
bus: wb-32-be
size: 0x80000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: tdc0
description: TDC0
address: 0x10000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: tdc1
description: TDC1
address: 0x20000
size: 0x10000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: mt
description: Mock Turtle
address: 0x40000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_tdc_x2_host_map.vhd 0 → 100644
View file @ 1feeb781
-- Do not edit. Generated on Tue Feb 16 11:24:52 2021 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl wrtd_tdc_x2_host_map.vhd -i wrtd_tdc_x2_host_map.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wrtd_tdc_x2_host_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the carrier metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- TDC0
tdc0_i : in t_wishbone_master_in;
tdc0_o : out t_wishbone_master_out;
-- TDC1
tdc1_i : in t_wishbone_master_in;
tdc1_o : out t_wishbone_master_out;
-- Mock Turtle
mt_i : in t_wishbone_master_in;
mt_o : out t_wishbone_master_out
);
end wrtd_tdc_x2_host_map;
architecture syn of wrtd_tdc_x2_host_map is
signal adr_int : std_logic_vector(18 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal tdc0_re : std_logic;
signal tdc0_we : std_logic;
signal tdc0_wt : std_logic;
signal tdc0_rt : std_logic;
signal tdc0_tr : std_logic;
signal tdc0_wack : std_logic;
signal tdc0_rack : std_logic;
signal tdc1_re : std_logic;
signal tdc1_we : std_logic;
signal tdc1_wt : std_logic;
signal tdc1_rt : std_logic;
signal tdc1_tr : std_logic;
signal tdc1_wack : std_logic;
signal tdc1_rack : std_logic;
signal mt_re : std_logic;
signal mt_we : std_logic;
signal mt_wt : std_logic;
signal mt_rt : std_logic;
signal mt_tr : std_logic;
signal mt_wack : std_logic;
signal mt_rack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(18 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(18 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wr_dat_d0;
-- Interface tdc0
tdc0_tr <= tdc0_wt or tdc0_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tdc0_rt <= '0';
tdc0_wt <= '0';
else
tdc0_rt <= (tdc0_rt or tdc0_re) and not tdc0_rack;
tdc0_wt <= (tdc0_wt or tdc0_we) and not tdc0_wack;
end if;
end if;
end process;
tdc0_o.cyc <= tdc0_tr;
tdc0_o.stb <= tdc0_tr;
tdc0_wack <= tdc0_i.ack and tdc0_wt;
tdc0_rack <= tdc0_i.ack and tdc0_rt;
tdc0_o.adr <= ((15 downto 0 => '0') & adr_int(15 downto 2)) & (1 downto 0 => '0');
tdc0_o.sel <= wr_sel_d0;
tdc0_o.we <= tdc0_wt;
tdc0_o.dat <= wr_dat_d0;
-- Interface tdc1
tdc1_tr <= tdc1_wt or tdc1_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tdc1_rt <= '0';
tdc1_wt <= '0';
else
tdc1_rt <= (tdc1_rt or tdc1_re) and not tdc1_rack;
tdc1_wt <= (tdc1_wt or tdc1_we) and not tdc1_wack;
end if;
end if;
end process;
tdc1_o.cyc <= tdc1_tr;
tdc1_o.stb <= tdc1_tr;
tdc1_wack <= tdc1_i.ack and tdc1_wt;
tdc1_rack <= tdc1_i.ack and tdc1_rt;
tdc1_o.adr <= ((15 downto 0 => '0') & adr_int(15 downto 2)) & (1 downto 0 => '0');
tdc1_o.sel <= wr_sel_d0;
tdc1_o.we <= tdc1_wt;
tdc1_o.dat <= wr_dat_d0;
-- Interface mt
mt_tr <= mt_wt or mt_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
mt_rt <= '0';
mt_wt <= '0';
else
mt_rt <= (mt_rt or mt_re) and not mt_rack;
mt_wt <= (mt_wt or mt_we) and not mt_wack;
end if;
end if;
end process;
mt_o.cyc <= mt_tr;
mt_o.stb <= mt_tr;
mt_wack <= mt_i.ack and mt_wt;
mt_rack <= mt_i.ack and mt_rt;
mt_o.adr <= ((14 downto 0 => '0') & adr_int(16 downto 2)) & (1 downto 0 => '0');
mt_o.sel <= wr_sel_d0;
mt_o.we <= mt_wt;
mt_o.dat <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, metadata_wack, tdc0_wack, tdc1_wack, mt_wack) begin
metadata_we <= '0';
tdc0_we <= '0';
tdc1_we <= '0';
mt_we <= '0';
case wr_adr_d0(18 downto 17) is
when "00" =>
case wr_adr_d0(16 downto 16) is
when "0" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_int <= metadata_wack;
when "1" =>
-- Submap tdc0
tdc0_we <= wr_req_d0;
wr_ack_int <= tdc0_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "01" =>
-- Submap tdc1
tdc1_we <= wr_req_d0;
wr_ack_int <= tdc1_wack;
when "10" =>
-- Submap mt
mt_we <= wr_req_d0;
wr_ack_int <= mt_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (adr_int, rd_req_int, metadata_i.dat, metadata_rack, tdc0_i.dat, tdc0_rack, tdc1_i.dat, tdc1_rack, mt_i.dat, mt_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
tdc0_re <= '0';
tdc1_re <= '0';
mt_re <= '0';
case adr_int(18 downto 17) is
when "00" =>
case adr_int(16 downto 16) is
when "0" =>
-- Submap metadata
metadata_re <= rd_req_int;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "1" =>
-- Submap tdc0
tdc0_re <= rd_req_int;
rd_dat_d0 <= tdc0_i.dat;
rd_ack_d0 <= tdc0_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "01" =>
-- Submap tdc1
tdc1_re <= rd_req_int;
rd_dat_d0 <= tdc1_i.dat;
rd_ack_d0 <= tdc1_rack;
when "10" =>
-- Submap mt
mt_re <= rd_req_int;
rd_dat_d0 <= mt_i.dat;
rd_ack_d0 <= mt_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
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