Merge branch '23-release-v2.0.1' into 'master'

Resolve "release v2.0.1" Closes #23 See merge request be-cem-edl/fec/hardware-modules/wrtd-reference-designs!13

Merge branch '23-release-v2.0.1' into 'master'
Resolve "release v2.0.1" Closes #23 See merge request be-cem-edl/fec/hardware-modules/wrtd-reference-designs!13
09862890 · Dimitris Lampridis · 4e137316 · 7ee4587f · 09862890 · 09862890
Commit 09862890 authored Dec 05, 2023 by Dimitris Lampridis
40 changed files
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -11,7 +11,58 @@ include:
  - project: 'be-cem-edl/evergreen/gitlab-ci'
    ref: master
    file: 'edl-gitlab-ci.yml'
-  - local: 'software/.gitlab-ci.yml'
  - local: 'hdl/testbench/.gitlab-ci.yml'
-  - local: 'hdl/syn/.gitlab-ci.yml'
  - local: 'pytest/.gitlab-ci.yml'
+
+fpga_synthesis:
+  extends: .synthesis-ise-14-7
+  allow_failure: true
+  needs: ["firmware_deliver"]
+  interruptible: true
+  parallel:
+    matrix:
+      - EDL_CI_SYN_SRC_PATH:
+        - hdl/syn/wrtd_ref_spec150t_adc
+        - hdl/syn/wrtd_ref_svec_adc_x2
+        - hdl/syn/wrtd_ref_svec_tdc_x2
+        - hdl/syn/wrtd_ref_svec_fd_x2
+        - hdl/syn/wrtd_ref_svec_tdc_fd
+
+software_build:
+  extends: .build_fec_os_sw
+  variables:
+    EDL_CI_SW_PATHS: software
+
+sim_fw_build:
+  extends: .build_urv_fw
+  needs: []
+  variables:
+    EXTRA2_CFLAGS: -DSIMULATION
+  script:
+    - make -C software/firmware
+  artifacts:
+    paths:
+      - software/firmware/**/*.bram
+
+firmware_build:
+  extends: .build_urv_fw
+  needs: []
+  variables:
+    EDL_CI_FW_PATHS: software/firmware
+
+# firmware needs to be in a specific location for our FPGA designs to be able to find it
+firmware_deliver:
+  stage: build
+  needs: ["firmware_build"]
+  variables:
+    _FW_ARTIFACT_PATH: '$CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR/firmware'
+    _FW_ARTIFACT: '$CI_PROJECT_NAME-firmware${CI_COMMIT_TAG:+-$CI_COMMIT_TAG}.tar.xz'
+    _FW_PROGRAMS: 'adc adc-x2 tdc tdc-x2 fd fd-x2'
+  script:
+    - export TMP_DIR=$(mktemp -d)
+    - tar xvf $_FW_ARTIFACT_PATH/$_FW_ARTIFACT -C $TMP_DIR/ --wildcards "*.bram" --strip-components 3
+    - for fw in $_FW_PROGRAMS; do mv $TMP_DIR/wrtd-rt-$fw.bram software/firmware/$fw/; done
+    - rm -r $TMP_DIR
+  artifacts:
+    paths:
+      - software/firmware/*/*.bram
--- a/CHANGELOG.rst
+++ b/CHANGELOG.rst
@@ -6,6 +6,25 @@
 Changelog
 =========

+2.1.0 - 2023-12-05
+==================
+
+Added
+-----
+- Support for VLAN tags
+
+Fixed
+-----
+- Endianess for SVEC-ADCx2
+- SPEC150T-ADC top-level driver (several issues)
+- Onewire signal in slot FMC1 for SVEC-FDx2
+
+Changed
+-------
+- Improved HDL partitioning and placement
+- Use common EDL CI pipelines for building and testing
+- Use latest releases for all dependencies
+
 2.0.0 - 2023-01-31
 ==================


--- a/fmc-delay-1ns-8cha @ 36abf5a2
+++ b/fmc-delay-1ns-8cha @ 36abf5a2
-Subproject commit 282bc2d858e88441d46ec04502ff531f073b88a2
+Subproject commit 36abf5a205739aa32272e5d745972fcad065667a
--- a/fmc-tdc @ f313382e
+++ b/fmc-tdc @ f313382e
-Subproject commit ee015a512a9c05c37834e007eba1ec2373038dcc
+Subproject commit f313382ebe572e95d4e9354f7e46a53028c4b1eb
--- a/general-cores @ 225dd70e
+++ b/general-cores @ 225dd70e
-Subproject commit b84c76be1eee1e987a0ff9947b5627d58e935f3f
+Subproject commit 225dd70e4cf4f93954414916f57ef1366e12e13b
--- a/gn4124-core @ ea7e8213
+++ b/gn4124-core @ ea7e8213
-Subproject commit d265dc5d0cbfe84bd5d310982e1a319a26bb53b2
+Subproject commit ea7e82131f0c228b9bdea4f9fb828dc14561c93e
--- a/mock-turtle @ a9b8030d
+++ b/mock-turtle @ a9b8030d
-Subproject commit 1f399c96dafafbe124540266b4b155d051c42dec
+Subproject commit a9b8030df55c174aabc72c4d6ff44224a09430fa
--- a/wrtd @ 08e5c265
+++ b/wrtd @ 08e5c265
-Subproject commit faf1ffbddc13d6f8b5ca86e378702403240ac493
+Subproject commit 08e5c265ec6e637e62d75ab24485233d69004f37
--- a/hdl/syn/.gitlab-ci.yml
+++ b/hdl/syn/.gitlab-ci.yml
-# SPDX-FileCopyrightText: 2022 CERN (home.cern)
-#
-# SPDX-License-Identifier: LGPL-2.1-or-later
-
-fpga_synthesis:
-  interruptible: true
-  stage: build
-  needs: []
-  tags:
-    - xilinx_ise
-    - "14.7"
-  variables:
-    _BITSTREAM_DEST: $CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR/bitstreams
-  parallel:
-    matrix:
-      - SYN_NAME:
-          - wrtd_ref_svec_adc_x2
-          - wrtd_ref_svec_fd_x2
-          - wrtd_ref_svec_tdc_x2
-          - wrtd_ref_spec150t_adc
-          - wrtd_ref_svec_tdc_fd
-  before_script:
-    - export TMP_DIR=$(mktemp -d)
-    - export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
-    - curl $PAK | tar xJ -C $TMP_DIR
-    - export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
-    - git submodule init && git submodule update
-  script:
-    - cd hdl/syn/"$SYN_NAME"/
-    - hdlmake
-    - make
-    - tar -cJf $SYN_NAME.tar.xz *.syr *.bld *.map *.mrp *.par *.twr *.bit *.bin
-    - mkdir -p $_BITSTREAM_DEST
-    - cp $SYN_NAME.tar.xz $_BITSTREAM_DEST
-    - |
-      if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
-      then
-        echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
-        exit 1
-      fi
-  artifacts:
-    name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
-    when: always
-    paths:
-      - $_BITSTREAM_DEST/*
--- a/hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
+++ b/hdl/syn/wrtd_ref_spec150t_adc/Manifest.py
@@ -30,7 +30,8 @@ modules = {
    ],
 }

-syn_pre_project_cmd = "make -C ../../../software/firmware/adc"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+# syn_pre_project_cmd = "make -C ../../../software/firmware/adc"

 # Do not fail during hdlmake fetch
 try:

--- a/hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
+++ b/hdl/syn/wrtd_ref_spec150t_adc/wrtd_ref_spec150t_adc.ucf
@@ -119,8 +119,9 @@ NET "aux_leds_o[*]" IOSTANDARD = "LVCMOS18";
 NET  "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/gc_sync_ffs_in" MAXDELAY = 1.5 ns;
 INST "cmp0_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0"       RLOC_ORIGIN = X68Y2;

-INST "inst_spec_base/gen_with_ddr.cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/cmp_cmd_fifo/U_Inferred_FIFO/U_FIFO_Ram/gen_single_clk.U_RAM_SC/Mram_ram1" LOC=RAMB16_X0Y44:RAMB16_X0Y54;
-INST "inst_spec_base/gen_with_ddr.cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/cmp_wr_fifo/U_Inferred_FIFO/U_FIFO_Ram/gen_single_clk.U_RAM_SC/Mram_ram1"  LOC=RAMB16_X0Y44:RAMB16_X0Y54;
+INST "inst_spec_base/gen_with_ddr.cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/cmp_wr_fifo/U_Inferred_FIFO/U_FIFO_Ram/gen_single_clk.U_RAM_SC/Mram_ram?" LOC=RAMB16_X0Y40:RAMB16_X0Y54;
+INST "inst_spec_base/gen_with_ddr.cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_?/cmp_cmd_fifo/U_Inferred_FIFO/U_FIFO_Ram/gen_single_clk.U_RAM_SC/Mram_ram1" LOC=RAMB16_X0Y40:RAMB16_X0Y54;
+INST "inst_spec_base/gen_with_ddr.cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_?/cmp_cmd_fifo/U_Inferred_FIFO/U_FIFO_Ram/gen_single_clk.U_RAM_SC/Mram_ram2" LOC=RAMB8_X0Y40:RAMB8_X0Y54;

 #----------------------------------------
 # IOB exceptions

--- a/hdl/syn/wrtd_ref_svec_adc_x2/Manifest.py
+++ b/hdl/syn/wrtd_ref_svec_adc_x2/Manifest.py
@@ -35,7 +35,8 @@ modules = {
    ],
 }

-syn_pre_project_cmd = "make -C ../../../software/firmware/adc-x2"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+# syn_pre_project_cmd = "make -C ../../../software/firmware/adc-x2"

 # Do not fail during hdlmake fetch
 try:

--- a/hdl/syn/wrtd_ref_svec_fd_x2/Manifest.py
+++ b/hdl/syn/wrtd_ref_svec_fd_x2/Manifest.py
@@ -39,7 +39,8 @@ modules = {
    ],
 }

-syn_pre_project_cmd = "make -C ../../../software/firmware/fd-x2"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+#syn_pre_project_cmd = "make -C ../../../software/firmware/fd-x2"

 # Do not fail during hdlmake fetch
 try:

--- a/hdl/syn/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.ucf
+++ b/hdl/syn/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.ucf
@@ -6,14 +6,44 @@
 # Timing constraints and exceptions
 #===============================================================================

-NET "fp_gpio3_b" TNM_NET = fp_gpio3;
-TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
+# Keep WR and MT away from FMC0 and FMC1, closer to the center of the FPGA
+#(FMC0 is on the top, FMC1 is on the bottom, WR I/O pins are on the center-right
+# of the device and MT does not have I/O).
+# Note: we do not specify the ranges using clock regions (even though they
+# correspond to clock regions) because for some reason PAR does not fully
+# respect the boundaries in that case (while it does if we do it explicitly for
+# SLICES, DSPs and BRAMs).

-NET "fmc0_fd_clk_ref_n_i" TNM_NET = fmc0_fd_clk_ref_n_i;
-TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50%;
+AREA_GROUP "fmc0" RANGE=SLICE_X116Y96:SLICE_X127Y189, SLICE_X0Y96:SLICE_X115Y191;
+AREA_GROUP "fmc0" RANGE=DSP48_X0Y24:DSP48_X3Y47;
+AREA_GROUP "fmc0" RANGE=RAMB16_X0Y48:RAMB16_X5Y94;
+AREA_GROUP "fmc0" RANGE=RAMB8_X0Y48:RAMB8_X5Y95;
+AREA_GROUP "fmc1" RANGE=SLICE_X12Y0:SLICE_X127Y95, SLICE_X0Y2:SLICE_X11Y95;
+AREA_GROUP "fmc1" RANGE=DSP48_X0Y0:DSP48_X3Y23;
+AREA_GROUP "fmc1" RANGE=RAMB16_X0Y0:RAMB16_X5Y46;
+AREA_GROUP "fmc1" RANGE=RAMB8_X0Y0:RAMB8_X5Y47;
+AREA_GROUP "away_from_fmcs" RANGE=SLICE_X0Y32:SLICE_X127Y159;
+AREA_GROUP "away_from_fmcs" RANGE=DSP48_X0Y8:DSP48_X3Y39;
+AREA_GROUP "away_from_fmcs" RANGE=RAMB16_X0Y16:RAMB16_X5Y78;
+AREA_GROUP "away_from_fmcs" RANGE=RAMB8_X0Y16:RAMB8_X5Y79;
+INST "inst_FineDelay_Core0/*" AREA_GROUP = "fmc0";
+INST "inst_FineDelay_Core1/*" AREA_GROUP = "fmc1";
+INST "cmp_mock_turtle/*" AREA_GROUP = "away_from_fmcs";
+INST "cmp_eth_endpoint/*" AREA_GROUP = "away_from_fmcs";
+INST "inst_svec_base/*/cmp_xwr_core/*" AREA_GROUP = "away_from_fmcs";

-NET "fmc1_fd_clk_ref_n_i" TNM_NET = fmc1_fd_clk_ref_n_i;
-TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
+#----------------------------------------
+# Clocks
+#----------------------------------------
+
+NET "fp_gpio3_b" TNM_NET = "fp_gpio3";
+TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50 %;
+
+NET "fmc0_fd_clk_ref_n_i" TNM_NET = "fmc0_fd_clk_ref_n_i";
+TIMESPEC TS_fmc0_fd_clk_ref_n_i = PERIOD "fmc0_fd_clk_ref_n_i" 8 ns HIGH 50 %;
+
+NET "fmc1_fd_clk_ref_n_i" TNM_NET = "fmc1_fd_clk_ref_n_i";
+TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50 %;

 #----------------------------------------
 # Cross-clock domain sync
@@ -22,20 +52,20 @@ TIMESPEC TS_fmc1_fd_clk_ref_n_i = PERIOD "fmc1_fd_clk_ref_n_i" 8 ns HIGH 50%;
 # IMPORTANT: timing constraints are also coming from SVEC base UCF files

 # Declaration of domains
-NET "dcm0_clk_ref_0" TNM_NET = fd0_clk;
-NET "dcm1_clk_ref_0" TNM_NET = fd1_clk;
+NET "dcm0_clk_ref_0" TNM_NET = "fd0_clk";
+NET "dcm1_clk_ref_0" TNM_NET = "fd1_clk";

 # Exceptions for crossings via gc_sync_ffs
-TIMEGRP "fd0_sync_ffs" = "sync_ffs" EXCEPT "fd0_clk";
-TIMEGRP "fd1_sync_ffs" = "sync_ffs" EXCEPT "fd1_clk";
+TIMEGRP fd0_sync_ffs =  "sync_ffs" EXCEPT  "fd0_clk";
+TIMEGRP fd1_sync_ffs =  "sync_ffs" EXCEPT  "fd1_clk";

-TIMESPEC TS_fd0_sync_ffs = FROM fd0_clk TO "fd0_sync_ffs" 8ns DATAPATHONLY;
-TIMESPEC TS_fd1_sync_ffs = FROM fd1_clk TO "fd1_sync_ffs" 8ns DATAPATHONLY;
+TIMESPEC TS_fd0_sync_ffs = FROM "fd0_clk" TO "fd0_sync_ffs" 8 ns DATAPATHONLY;
+TIMESPEC TS_fd1_sync_ffs = FROM "fd1_clk" TO "fd1_sync_ffs" 8 ns DATAPATHONLY;

 # Exceptions for crossings via gc_sync_register

-TIMEGRP "fd0_sync_reg" = "sync_reg" EXCEPT "fd0_clk";
-TIMEGRP "fd1_sync_reg" = "sync_reg" EXCEPT "fd1_clk";
+TIMEGRP fd0_sync_reg =  "sync_reg" EXCEPT  "fd0_clk";
+TIMEGRP fd1_sync_reg =  "sync_reg" EXCEPT  "fd1_clk";

-TIMESPEC TS_fd0_sync_reg = FROM fd0_clk TO "fd0_sync_reg" 8ns DATAPATHONLY;
-TIMESPEC TS_fd1_sync_reg = FROM fd1_clk TO "fd1_sync_reg" 8ns DATAPATHONLY;
+TIMESPEC TS_fd0_sync_reg = FROM "fd0_clk" TO "fd0_sync_reg" 8 ns DATAPATHONLY;
+TIMESPEC TS_fd1_sync_reg = FROM "fd1_clk" TO "fd1_sync_reg" 8 ns DATAPATHONLY;
--- a/hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/syn/wrtd_ref_svec_tdc_fd/Manifest.py
@@ -35,10 +35,11 @@ modules = {
    ],
 }

-syn_pre_project_cmd = (
-    "make -C ../../../software/firmware/tdc;"
-    "make -C ../../../software/firmware/fd"
-)
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+# syn_pre_project_cmd = (
+#    "make -C ../../../software/firmware/tdc;"
+#    "make -C ../../../software/firmware/fd"
+#)

 # Do not fail during hdlmake fetch
 try:

--- a/hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
+++ b/hdl/syn/wrtd_ref_svec_tdc_fd/wrtd_ref_svec_tdc_fd.ucf
@@ -338,6 +338,38 @@ NET "fmc1_fd_dmtd_fb_in_i" IOSTANDARD = "LVCMOS25";
 # Timing constraints and exceptions
 #===============================================================================

+# Keep WR and MT away from FMC0 and FMC1, closer to the center of the FPGA
+#(FMC0 is on the top, FMC1 is on the bottom, WR I/O pins are on the center-right
+# of the device and MT does not have I/O).
+# Note: we do not specify the ranges using clock regions (even though they
+# correspond to clock regions) because for some reason PAR does not fully
+# respect the boundaries in that case (while it does if we do it explicitly for
+# SLICES, DSPs and BRAMs).
+
+
+AREA_GROUP "fmc0" RANGE=SLICE_X116Y96:SLICE_X127Y189, SLICE_X0Y96:SLICE_X115Y191;
+AREA_GROUP "fmc0" RANGE=DSP48_X0Y24:DSP48_X3Y47;
+AREA_GROUP "fmc0" RANGE=RAMB16_X0Y48:RAMB16_X5Y94;
+AREA_GROUP "fmc0" RANGE=RAMB8_X0Y48:RAMB8_X5Y95;
+AREA_GROUP "fmc1" RANGE=SLICE_X12Y0:SLICE_X127Y95, SLICE_X0Y2:SLICE_X11Y95;
+AREA_GROUP "fmc1" RANGE=DSP48_X0Y0:DSP48_X3Y23;
+AREA_GROUP "fmc1" RANGE=RAMB16_X0Y0:RAMB16_X5Y46;
+AREA_GROUP "fmc1" RANGE=RAMB8_X0Y0:RAMB8_X5Y47;
+AREA_GROUP "away_from_fmcs" RANGE=SLICE_X0Y32:SLICE_X127Y159;
+AREA_GROUP "away_from_fmcs" RANGE=DSP48_X0Y8:DSP48_X3Y39;
+AREA_GROUP "away_from_fmcs" RANGE=RAMB16_X0Y16:RAMB16_X5Y78;
+AREA_GROUP "away_from_fmcs" RANGE=RAMB8_X0Y16:RAMB8_X5Y79;
+INST "U_TDC_Core/*" AREA_GROUP = "fmc0";
+INST "U_FineDelay_Core/*" AREA_GROUP = "fmc1";
+INST "cmp_fmc1_wb_mux/*" AREA_GROUP = "fmc1";
+INST "cmp_mock_turtle/*" AREA_GROUP = "away_from_fmcs";
+INST "cmp_eth_endpoint/*" AREA_GROUP = "away_from_fmcs";
+INST "inst_svec_base/*/cmp_xwr_core/*" AREA_GROUP = "away_from_fmcs";
+
+#----------------------------------------
+# Clocks
+#----------------------------------------
+
 NET "fp_gpio3_b" TNM_NET = fp_gpio3;
 TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;


--- a/hdl/syn/wrtd_ref_svec_tdc_x2/Manifest.py
+++ b/hdl/syn/wrtd_ref_svec_tdc_x2/Manifest.py
@@ -39,7 +39,8 @@ modules = {
    ],
 }

-syn_pre_project_cmd = "make -C ../../../software/firmware/tdc-x2"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+# syn_pre_project_cmd = "make -C ../../../software/firmware/tdc-x2"

 # Do not fail during hdlmake fetch
 try:

--- a/hdl/testbench/.gitlab-ci.yml
+++ b/hdl/testbench/.gitlab-ci.yml
@@ -6,7 +6,7 @@ hdl_simulation:
  interruptible: true
  stage: build
  when: manual
-  needs: []
+  needs: [sim_fw_build]
  tags:
    - questasim
    - "10.5c"
@@ -17,9 +17,6 @@ hdl_simulation:
          - wrtd_ref_svec_tdc_fd
  before_script:
    - export TMP_DIR=$(mktemp -d)
-    - export PAK=https://ohwr-packages.web.cern.ch/ohwr-packages/riscv_toolchains/riscv-centos7.tar.xz
-    - curl $PAK | tar xJ -C $TMP_DIR
-    - export CROSS_COMPILE_TARGET=$TMP_DIR/riscv/bin/riscv32-elf-
    - git submodule init && git submodule update
  script:
    - cd hdl/testbench/"$SIM_NAME"/

--- a/hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
+++ b/hdl/testbench/wrtd_ref_spec150t_adc/Manifest.py
@@ -16,7 +16,8 @@ vcom_opt   = "-93 -mixedsvvh"
 if locals().get('fetchto', None) is None:
    fetchto = "../../../dependencies"

-sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware/adc"
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../software/firmware/adc"

 include_dirs = [
    fetchto + "/wrtd/hdl/testbench/include",

--- a/hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
+++ b/hdl/testbench/wrtd_ref_svec_tdc_fd/Manifest.py
@@ -21,11 +21,12 @@ if locals().get('fetchto', None) is None:
 import os
 fetchto = os.path.abspath(fetchto)

-sim_pre_cmd = (
-    "export EXTRA2_CFLAGS='-DSIMULATION';"
-    "make -C ../../../software/firmware/tdc;"
-    "make -C ../../../software/firmware/fd"
-)
+# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
+#sim_pre_cmd = (
+#    "export EXTRA2_CFLAGS='-DSIMULATION';"
+#    "make -C ../../../software/firmware/tdc;"
+#    "make -C ../../../software/firmware/fd"
+#)

 include_dirs = [
    fetchto + "/wrtd/hdl/testbench/include",

--- a/hdl/top/wrtd_ref_svec_adc_x2/wrtd_ref_svec_adc_x2.vhd
+++ b/hdl/top/wrtd_ref_svec_adc_x2/wrtd_ref_svec_adc_x2.vhd
@@ -693,7 +693,7 @@ begin -- architecture arch
        g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
        g_SPARTAN6_USE_PLL   => TRUE,
        g_FMC_ADC_NR         => I,
--        g_BYTE_SWAP          => True,
+        g_BYTE_SWAP          => TRUE,
        g_WB_MODE            => PIPELINED,
        g_WB_GRANULARITY     => BYTE)
      port map (

--- a/hdl/top/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.vhd
+++ b/hdl/top/wrtd_ref_svec_fd_x2/wrtd_ref_svec_fd_x2.vhd
@@ -762,7 +762,7 @@ begin  -- architecture arch
  fmc0_fd_tdc_data_in <= fmc0_fd_tdc_d_b;

  fmc0_fd_onewire_b <= '0' when fmc0_fd_owr_en = '1' else 'Z';
-  fmc0_fd_owr_in    <= fmc1_fd_onewire_b;
+  fmc0_fd_owr_in    <= fmc0_fd_onewire_b;

  -----------------------------------------------------------------------------
  -- FMC FDELAY (SVEC slot #2)

--- a/pytest/.gitlab-ci.yml
+++ b/pytest/.gitlab-ci.yml
@@ -2,13 +2,22 @@
 #
 # SPDX-License-Identifier: LGPL-2.1-or-later

+.module_cleanup: &module_cleanup
+    - rmmod wrtd_ref_svec_adc_x2 || true
+    - rmmod wrtd_ref_svec_tdc_x2 || true
+    - rmmod wrtd_ref_svec_fd_x2 || true
+    - rmmod mockturtle || true
+    - rmmod fmc-adc-100m14b4ch || true
+    - rmmod svec-fmc-carrier || true
+
 Full test on FEC:
  stage: validate
+  allow_failure: true
  needs:
-    - "fpga_synthesis: [wrtd_ref_svec_adc_x2]"
-    - "fpga_synthesis: [wrtd_ref_svec_fd_x2]"
-    - "fpga_synthesis: [wrtd_ref_svec_tdc_x2]"
-    - "build software"
+    - "fpga_synthesis: [hdl/syn/wrtd_ref_svec_adc_x2]"
+    - "fpga_synthesis: [hdl/syn/wrtd_ref_svec_fd_x2]"
+    - "fpga_synthesis: [hdl/syn/wrtd_ref_svec_tdc_x2]"
+    - "software_build: [production]"
  tags:
    - fec-runner
    - wrtd-ci-tester
@@ -17,41 +26,70 @@ Full test on FEC:
    ADC_PID:  "57544e05"
    TDC_PID:  "57544e03"
    FD_PID:   "57544e04"
-    _BITSTREAM_DEST: $CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR/bitstreams
-  script:
-    - rmmod wrtd_ref_svec_adc_x2 || true
-    - rmmod wrtd_ref_svec_tdc_x2 || true
-    - rmmod wrtd_ref_svec_fd_x2 || true
+    _BASE_DEST: $CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR
+    _BITSTREAM_DEST: $_BASE_DEST/bitstreams
+    _SW_ARTIFACT_PATH: $_BASE_DEST/software
+    _SW_ARTIFACT: '$CI_PROJECT_NAME-software-production${CI_COMMIT_TAG:+-$CI_COMMIT_TAG}.tar.xz'
+    _DEPLOY: /acc/local/L867/drv
+    _VER_ADCLIB: "4.0"
+    _VER_WRTD: "1.2"
+    _LIB_ADCLIB: $_DEPLOY/adc-lib/$_VER_ADCLIB/lib
+    _LIB_WRTD: $_DEPLOY/wrtd/$_VER_WRTD/lib
+    _BIN_WRTD: $_DEPLOY/wrtd/$_VER_WRTD/bin
+    _PY_WRTD: $_LIB_WRTD/python/site-packages
+  before_script:
+    - *module_cleanup
    - export TMP_DIR=$(mktemp -d)
-    - mkdir -p $TMP_DIR/lib/modules
-    - cp -r /usr/local/lib/modules/$(uname -r) $TMP_DIR/lib/modules
-    - cp software/drivers/*.ko $TMP_DIR/lib/modules/$(uname -r)/extra/cern/
-    - export MODPROBE_ROOT=$TMP_DIR
+    - mkdir -p $TMP_DIR/usr/lib/modules
+    - cp -r /usr/local/lib/modules/$(uname -r) $TMP_DIR/usr/lib/modules
+    - find $TMP_DIR/usr/lib/modules -name wrtd-ref-*.ko -delete
+    - tar xvf $_SW_ARTIFACT_PATH/$_SW_ARTIFACT -C $TMP_DIR/
+    - export MODPROBE_ROOT=$TMP_DIR/usr
    - depmod -b $MODPROBE_ROOT
+    - modprobe -d $MODPROBE_ROOT -v mockturtle
+    - modprobe -d $MODPROBE_ROOT -v htvic
+    - modprobe -d $MODPROBE_ROOT -v i2c-ocores
+    - modprobe -d $MODPROBE_ROOT -v i2c-mux
+    - modprobe -d $MODPROBE_ROOT -v zio
+    - modprobe -d $MODPROBE_ROOT -v zio-buf-vmalloc
+    - modprobe -d $MODPROBE_ROOT -v fmc-adc-100m14b4ch version_ignore=1
+    - modprobe -v at24
    - export FIRMWARE_PATH=$TMP_DIR/bitstreams
    - mkdir -p $FIRMWARE_PATH
-    - tar xf $_BITSTREAM_DEST/wrtd_ref_svec_adc_x2.tar.xz -C $FIRMWARE_PATH
-    - tar xf $_BITSTREAM_DEST/wrtd_ref_svec_fd_x2.tar.xz -C $FIRMWARE_PATH
-    - tar xf $_BITSTREAM_DEST/wrtd_ref_svec_tdc_x2.tar.xz -C $FIRMWARE_PATH
+    - tar xf $_BITSTREAM_DEST/wrtd_ref_svec_adc_x2${CI_COMMIT_TAG:+-$CI_COMMIT_TAG}.tar.xz -C $FIRMWARE_PATH
+    - tar xf $_BITSTREAM_DEST/wrtd_ref_svec_fd_x2${CI_COMMIT_TAG:+-$CI_COMMIT_TAG}.tar.xz -C $FIRMWARE_PATH
+    - tar xf $_BITSTREAM_DEST/wrtd_ref_svec_tdc_x2${CI_COMMIT_TAG:+-$CI_COMMIT_TAG}.tar.xz -C $FIRMWARE_PATH
    - ln -sf $FIRMWARE_PATH/wrtd_ref_svec_adc_x2.bin $FIRMWARE_PATH/svec-wrtd-ref-adc-x2.bin
    - ln -sf $FIRMWARE_PATH/wrtd_ref_svec_fd_x2.bin $FIRMWARE_PATH/svec-wrtd-ref-fd-x2.bin
    - ln -sf $FIRMWARE_PATH/wrtd_ref_svec_tdc_x2.bin $FIRMWARE_PATH/svec-wrtd-ref-tdc-x2.bin
    - /usr/local/drivers/scripts/wrtd_install.sh wrtd-svec-adc-x2 -L2
    - /usr/local/drivers/scripts/wrtd_install.sh wrtd-svec-fd-x2 -L1
    - /usr/local/drivers/scripts/wrtd_install.sh wrtd-svec-tdc-x2 -L0
+    - source /acc/local/share/python/acc-py/base/pro/setup.sh
+    - acc-py venv $TMP_DIR/venv
+    - source $TMP_DIR/venv/bin/activate
+    - pip install -r pytest/requirements.txt
+    - pip install $_LIB_ADCLIB/python/PyAdcLib-*.whl
+    - export LD_LIBRARY_PATH=$_LIB_ADCLIB:$_LIB_WRTD
+    - export PYTHONPATH=$_PY_ADCLIB:$_PY_WRTD
+  script:
    - tail -n +1 /sys/kernel/debug/svec-vme.*/fpga_device_metadata
    - tail -n +1 /sys/kernel/debug/svec-vme.*/svec-vme.*-fpga/build_info
-    - /usr/local/bin/wrtd-tool list-nodes
+    - $_BIN_WRTD/wrtd-tool list-nodes
    - export ADC_NODE=$(ls -d /sys/bus/platform/devices/id\:$CERN_VID$ADC_PID.*/mock-turtle.* | cut -d '.' -f 4)
    - export TDC_NODE=$(ls -d /sys/bus/platform/devices/id\:$CERN_VID$TDC_PID.*/mock-turtle.* | cut -d '.' -f 4)
    - export FD_NODE=$(ls -d /sys/bus/platform/devices/id\:$CERN_VID$FD_PID.*/mock-turtle.* | cut -d '.' -f 4)
+    - export ADC_ID1=$(ls -d /sys/bus/platform/devices/id\:$CERN_VID$ADC_PID.*/fmc-adc-100m.*.auto/fmc-slot-*.1 | cut -d '.' -f 4)
+    - export ADC_ID2=$(ls -d /sys/bus/platform/devices/id\:$CERN_VID$ADC_PID.*/fmc-adc-100m.*.auto/fmc-slot-*.2 | cut -d '.' -f 4)
+    - env | grep -E "ADC|TDC|FD"
    - sleep 60
-    - /usr/local/bin/wrtd-tool sys-info $ADC_NODE
-    - /usr/local/bin/wrtd-tool sys-info $TDC_NODE
-    - /usr/local/bin/wrtd-tool sys-info $FD_NODE
-    - export LD_LIBRARY_PATH=/user/dlamprid/wrtd/lib
+    - $_BIN_WRTD/wrtd-tool sys-info $ADC_NODE
+    - $_BIN_WRTD/wrtd-tool sys-info $TDC_NODE
+    - $_BIN_WRTD/wrtd-tool sys-info $FD_NODE
    - cd pytest
-    - /user/dlamprid/wrtd/pytest_venv/bin/python -m pytest --adc-node $ADC_NODE --tdc-node $TDC_NODE --fd-node $FD_NODE --fmc-adc-id1 4 --fmc-adc-id2 5 --junitxml=./pytest.xml
+    - python3 -m pytest --adc-node $ADC_NODE --tdc-node $TDC_NODE --fd-node $FD_NODE --fmc-adc-id1 $ADC_ID1 --fmc-adc-id2 $ADC_ID2 --junitxml=./pytest.xml
+  after_script:
+    - *module_cleanup
  artifacts:
    when: always
    paths:

--- a/pytest/requirements.txt
+++ b/pytest/requirements.txt
@@ -3,3 +3,4 @@
 # SPDX-License-Identifier: LGPL-2.1-or-later

 pytest
+decorator
--- a/pytest/tests/WrtdTestHelper.py
+++ b/pytest/tests/WrtdTestHelper.py
@@ -14,7 +14,13 @@ class FmcAdc100m(PyFmcAdc100m14b4ch):
            conf = PyAdcConf(PyAdcConf.ADC_CONF_TYPE_CHN, ch)
            conf.value_set(PyAdcConf.ADC_CONF_CHN_RANGE,
                           self.ADC_CONF_100M14B4CHA_CHN_RANGE_10V)
-            conf.value_set(PyAdcConf.ADC_CONF_CHN_TERMINATION, 1)
+            # Last channel is shared with external trigger input in our
+            # hardware testbed. The external trigger input is already
+            # terminated.
+            if ch == 3:
+                conf.value_set(PyAdcConf.ADC_CONF_CHN_TERMINATION, 0)
+            else:
+                conf.value_set(PyAdcConf.ADC_CONF_CHN_TERMINATION, 1)
            conf.value_set(PyAdcConf.ADC_CONF_CHN_OFFSET, 0)
            conf.value_set(PyAdcConf.ADC_CONF_CHN_SATURATION, 0x7FFF)
            self.apply_config(conf, 0)
@@ -36,7 +42,7 @@ class FmcAdc100m(PyFmcAdc100m14b4ch):

    def enable_int_trigger(self, ch):
        conf = PyAdcConf(PyAdcConf.ADC_CONF_TYPE_TRG_THR, ch)
-        conf.value_set(PyAdcConf.ADC_CONF_TRG_THR_THRESHOLD, 2000)
+        conf.value_set(PyAdcConf.ADC_CONF_TRG_THR_THRESHOLD, 5000)
        conf.value_set(PyAdcConf.ADC_CONF_TRG_THR_ENABLE, 1)
        self.apply_config(conf, 0)


--- a/pytest/tests/conftest.py
+++ b/pytest/tests/conftest.py
@@ -11,10 +11,10 @@ def pytest_addoption(parser):
                     help="WRTD node ID for the TDC board")
    parser.addoption("--fd-node", required=True, type=int,
                     help="WRTD node ID for the FD board")
-    parser.addoption("--fmc-adc-id1", required=True, type=lambda x : int(x, 16),
-                     help="FMC-ADC ID (in hex) for the ADC in FMC slot 1")
-    parser.addoption("--fmc-adc-id2", required=True, type=lambda x : int(x, 16),
-                     help="FMC-ADC ID (in hex) for the ADC in FMC slot 2")
+    parser.addoption("--fmc-adc-id1", required=True, type=int,
+                     help="FMC-ADC ID for the ADC in FMC slot 1")
+    parser.addoption("--fmc-adc-id2", required=True, type=int,
+                     help="FMC-ADC ID for the ADC in FMC slot 2")

 def pytest_configure(config):
    pytest.adc_node = config.getoption("--adc-node")

--- a/software/.gitlab-ci.yml
+++ b/software/.gitlab-ci.yml
-# SPDX-FileCopyrightText: 2022 CERN (home.cern)
-#
-# SPDX-License-Identifier: LGPL-2.1-or-later
-
-build software:
-  interruptible: true
-  stage: build
-  image:
-    name: gitlab-registry.cern.ch/be-cem-edl/evergreen/gitlab-ci/build-fec-sw:latest
-  needs: []
-  script:
-    - git submodule update --init --depth 1
-    - make -C dependencies/fmc-sw/drivers/fmc/
-    - make -C software
-  artifacts:
-    name: "software-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
-    paths:
-      - software/drivers/*.ko
-      - software/firmware/*/*.elf
-      - software/firmware/*/*.bin
-      - software/firmware/*/*.bram
--- a/software/Makefile
+++ b/software/Makefile
@@ -9,7 +9,7 @@ CURDIR:=$(shell /bin/pwd)
 REPO_PARENT ?= $(CURDIR)/..
 -include $(REPO_PARENT)/parent_common.mk

-DIRS = drivers firmware
+DIRS = drivers

 all clean install: $(DIRS)


--- a/software/drivers/.gitignore
+++ b/software/drivers/.gitignore
@@ -11,5 +11,6 @@
 *.ko.cmd
 *.mod
 *.mod.cmd
+*.cmd
 Module.symvers
-modules.order
\ No newline at end of file
+modules.order
--- a/software/drivers/Makefile
+++ b/software/drivers/Makefile
@@ -10,7 +10,9 @@
 REPO_PARENT ?= $(shell /bin/pwd)/../..
 -include $(REPO_PARENT)/parent_common.mk

-KERNELSRC ?= /lib/modules/$(shell uname -r)/build
+KVERSION ?= $(shell uname -r)
+KERNELSRC ?= /lib/modules/$(KVERSION)/build
+INSTALL_MOD_PATH ?= /

 DRV_VERSION := $(shell git describe --always --dirty --long --tags)

@@ -23,19 +25,17 @@ FMC_EXTRA_SYMBOLS-y = $(FMC_ABS)/drivers/fmc/Module.symvers
 ADC_ABS ?= $(abspath $(FETCHTO)/fmc-adc-100m14b4cha)

 all: modules
+install: modules_install

 .PHONY: all modules clean help install modules_install

-modules help modules_install:
+clean help modules: fmc-sw
 	$(MAKE) -C $(KERNELSRC) M=$(shell pwd) DRV_VERSION=$(DRV_VERSION) \
 		FMC_ABS=$(FMC_ABS) ADC_ABS=$(ADC_ABS) \
 		FMC_EXTRA_SYMBOLS-y=$(FMC_EXTRA_SYMBOLS-y) $@

-install:
-	$(MAKE) -C $(KERNELSRC) M=$(shell pwd) DRV_VERSION=$(DRV_VERSION) \
-		FMC_ABS=$(FMC_ABS) ADC_ABS=$(ADC_ABS) modules_install
+fmc-sw:
+	$(MAKE) -C $(FMC)/drivers/fmc

-# be able to run the "clean" rule even if $(KERNELSRC) is not valid
-clean:
-	rm -rf *.o *~  .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \
-                         Module.markers modules.order
+modules_install: modules
+	$(MAKE) -C $(KERNELSRC) M=$(shell /bin/pwd) INSTALL_MOD_PATH=$(INSTALL_MOD_PATH) $@
--- a/software/drivers/wrtd-ref-spec150t-adc-core.c
+++ b/software/drivers/wrtd-ref-spec150t-adc-core.c
@@ -9,9 +9,13 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/core.h>
-#include <linux/mod_devicetable.h>
+#include <linux/fmc.h>
+
+#include "platform_data/fmc-adc-100m14b4cha.h"

 enum wrtd_spec150t_adc_dev_offsets {
+	FA_SPEC_DBL_ADC_META_START = 0x00000000,
+	FA_SPEC_DBL_ADC_META_END   = 0x00000040,
 	WRTD_SPEC150T_ADC_FA100_MEM_START = 0x00002000,
 	WRTD_SPEC150T_ADC_FA100_MEM_END = 0x00003A00,
 	WRTD_SPEC150T_ADC_TRTL_MEM_START = 0x0001E000,
@@ -24,6 +28,13 @@ enum spec_fpga_mfd_devs_enum {
 	WRTD_SPEC150T_ADC_MFD_FA100,
 };

+static const struct fmc_adc_platform_data fmc_adc_pdata = {
+	.flags = 0,
+	.calib_trig_time = 0,
+	.calib_trig_threshold = 0,
+	.calib_trig_internal = 0,
+};
+
 static struct resource wrtd_spec150t_adc_fa100_res[] = {
 	{
 		.name = "fmc-adc-100m14b4ch-mem",
@@ -36,6 +47,16 @@ static struct resource wrtd_spec150t_adc_fa100_res[] = {
 		.start = 0,
 		.end = 0,
 	},
+	{
+		.name = "fmc-adc-dma",
+		.flags = IORESOURCE_DMA,
+	},
+	{
+		.name = "fmc-adc-meta",
+		.flags = IORESOURCE_MEM,
+		.start = FA_SPEC_DBL_ADC_META_START,
+		.end = FA_SPEC_DBL_ADC_META_END,
+	},
 };

 static struct resource wrtd_spec150t_adc_trtl_res[] = {
@@ -72,9 +93,9 @@ static const struct mfd_cell wrtd_spec150t_adc_mfd_devs[] = {
 		.resources = wrtd_spec150t_adc_trtl_res,
 	},
 	[WRTD_SPEC150T_ADC_MFD_FA100] = {
-		.name = "adc-100m-spec",
-		.platform_data = NULL,
-		.pdata_size = 0,
+		.name = "fmc-adc-100m",
+		.platform_data = (void *)&fmc_adc_pdata,
+		.pdata_size = sizeof(fmc_adc_pdata),
 		.num_resources = ARRAY_SIZE(wrtd_spec150t_adc_fa100_res),
 		.resources = wrtd_spec150t_adc_fa100_res,
 	},
@@ -83,8 +104,24 @@ static const struct mfd_cell wrtd_spec150t_adc_mfd_devs[] = {

 static int wrtd_spec150t_adc_probe(struct platform_device *pdev)
 {
-	struct resource *rmem;
+	struct resource *rmem, *rdma;
 	int irq;
+	struct fmc_slot *slot;
+	bool present;
+
+	slot = fmc_slot_get(pdev->dev.parent, 1);
+	if (IS_ERR(slot)) {
+		dev_err(&pdev->dev, "Can't find FMC slot 1 err: %ld\n",
+			PTR_ERR(slot));
+		return PTR_ERR(slot);
+	}
+	present = fmc_slot_present(slot);
+	fmc_slot_put(slot);
+	if (!present) {
+		dev_err(&pdev->dev,
+			"FMC slot: 1, not present\n");
+		return -ENODEV;
+	}

 	rmem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!rmem) {
@@ -98,6 +135,13 @@ static int wrtd_spec150t_adc_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}

+	rdma = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+	if (!rdma) {
+		dev_err(&pdev->dev, "Missing DMA engine\n");
+		return -EINVAL;
+	}
+	wrtd_spec150t_adc_fa100_res[2].start = rdma->start;
+
 	/*
 	 * We know that this design uses the HTVIC IRQ controller.
 	 * This IRQ controller has a linear mapping, so it is enough

--- a/software/drivers/wrtd-ref-svec-adc-x2-core.c
+++ b/software/drivers/wrtd-ref-svec-adc-x2-core.c
@@ -132,6 +132,8 @@ static struct resource wrtd_svec_adc_x2_res2[] = {
 	},
 };

+#define ADC_RES_N ARRAY_SIZE(wrtd_svec_adc_x2_res1)
+
 static struct resource wrtd_svec_adc_x2_trtl_res[] = {
 	{
 		.name  = "mock-turtle-mem",
@@ -157,6 +159,8 @@ static struct resource wrtd_svec_adc_x2_trtl_res[] = {
 	},
 };

+#define MT_RES_N ARRAY_SIZE(wrtd_svec_adc_x2_trtl_res)
+
 static struct resource *wrtd_svec_adc_x2_res[] = {
 	wrtd_svec_adc_x2_res1,
 	wrtd_svec_adc_x2_res2,
@@ -192,8 +196,7 @@ static int wrtd_svec_adc_x2_probe(struct platform_device *pdev)
 		return -ENOMEM;

 	for (i = 0; i < SVEC_FMC_SLOTS; ++i) {
-		unsigned int res_n = ARRAY_SIZE(wrtd_svec_adc_x2_res1);
-		struct resource res[res_n];
+		struct resource res[ADC_RES_N];
 		struct fmc_slot *slot = fmc_slot_get(pdev->dev.parent, i + 1);
 		int present;
 		struct resource *rdma;
@@ -229,8 +232,7 @@ static int wrtd_svec_adc_x2_probe(struct platform_device *pdev)
 		pdev_data->adc[i] = platform_device_register_resndata_mask(&pdev->dev,
 									   "fmc-adc-100m",
 									   PLATFORM_DEVID_AUTO,
-									   res,
-									   res_n,
+									   res, ADC_RES_N,
 									   &wrtd_svec_adc_x2_pdata[i],
 									   sizeof(wrtd_svec_adc_x2_pdata[i]),
 									   DMA_BIT_MASK(32));
@@ -244,8 +246,7 @@ static int wrtd_svec_adc_x2_probe(struct platform_device *pdev)

 	/* Mockturtle */
 	{
-		unsigned int res_n = ARRAY_SIZE(wrtd_svec_adc_x2_trtl_res);
-		struct resource res[res_n];
+		struct resource res[MT_RES_N];

 		memcpy(res, wrtd_svec_adc_x2_trtl_res, sizeof(res));

@@ -259,7 +260,7 @@ static int wrtd_svec_adc_x2_probe(struct platform_device *pdev)
 		pdev_data->trtl = platform_device_register_resndata(&pdev->dev,
 								    "mock-turtle",
 								    PLATFORM_DEVID_AUTO,
-								    res, res_n,
+								    res, MT_RES_N,
 								    NULL, 0);
 		if (IS_ERR(pdev_data->trtl)) {
 			dev_err(&pdev->dev,

--- a/software/firmware/adc-x2/wrtd-rt-adc-x2.c
+++ b/software/firmware/adc-x2/wrtd-rt-adc-x2.c
@@ -22,6 +22,11 @@
 #define WRTD_LOCAL_TX 1
 #define WRTD_LOCAL_RX 1

+/* WRPC simulation SW does not support VLANs */
+#ifndef SIMULATION
+#define WRTD_NET_VLAN
+#endif
+
 #include "wrtd-rt-common.h"

 #include "wrtd-adcout.c"

--- a/software/firmware/adc/wrtd-adcin.c
+++ b/software/firmware/adc/wrtd-adcin.c
@@ -85,7 +85,6 @@ static void adcin_input(struct wrtd_adcin_dev *adcin)
                        ev.id.c[4] = '1';
                        ev.id.c[5] = '0' + ch - 9;
                }
-                ev.flags = 0;

                wrtd_log(WRTD_LOG_MSG_EV_GENERATED,
                         WRTD_LOG_GENERATED_DEVICE + (i * 8),

--- a/software/firmware/adc/wrtd-rt-adc.c
+++ b/software/firmware/adc/wrtd-rt-adc.c
@@ -25,6 +25,11 @@
 #define WRTD_LOCAL_TX 1
 #define WRTD_LOCAL_RX 1

+/* WRPC simulation SW does not support VLANs */
+#ifndef SIMULATION
+#define WRTD_NET_VLAN
+#endif
+
 #include "wrtd-rt-common.h"

 #include "wrtd-adcout.c"

--- a/software/firmware/fd-x2/wrtd-rt-fd-x2.c
+++ b/software/firmware/fd-x2/wrtd-rt-fd-x2.c
@@ -23,6 +23,11 @@
 #define WRTD_LOCAL_TX 1
 #define WRTD_LOCAL_RX 0

+/* WRPC simulation SW does not support VLANs */
+#ifndef SIMULATION
+#define WRTD_NET_VLAN
+#endif
+
 #include "wrtd-rt-common.h"

 #include "wrtd-fd.c"

--- a/software/firmware/fd/wrtd-rt-fd.c
+++ b/software/firmware/fd/wrtd-rt-fd.c
@@ -28,6 +28,11 @@
 #define WRTD_LOCAL_TX 1
 #define WRTD_LOCAL_RX 0

+/* WRPC simulation SW does not support VLANs */
+#ifndef SIMULATION
+#define WRTD_NET_VLAN
+#endif
+
 #include "wrtd-rt-common.h"

 #include "wrtd-fd.c"

--- a/software/firmware/tdc-x2/wrtd-rt-tdc-x2.c
+++ b/software/firmware/tdc-x2/wrtd-rt-tdc-x2.c
@@ -26,6 +26,11 @@
 #define WRTD_LOCAL_TX 0
 #define WRTD_LOCAL_RX 1

+/* WRPC simulation SW does not support VLANs */
+#ifndef SIMULATION
+#define WRTD_NET_VLAN
+#endif
+
 #include "wrtd-rt-common.h"

 #include "wrtd-tdc.c"

--- a/software/firmware/tdc/wrtd-rt-tdc.c
+++ b/software/firmware/tdc/wrtd-rt-tdc.c
@@ -22,6 +22,11 @@
 #define WRTD_LOCAL_TX 0
 #define WRTD_LOCAL_RX 1

+/* WRPC simulation SW does not support VLANs */
+#ifndef SIMULATION
+#define WRTD_NET_VLAN
+#endif
+
 #include "wrtd-rt-common.h"

 #include "wrtd-tdc.c"

--- a/software/firmware/tdc/wrtd-tdc.c
+++ b/software/firmware/tdc/wrtd-tdc.c
@@ -317,7 +317,6 @@ static void tdc_input(struct wrtd_tdc_dev *tdc)
                /* channel starts from 0. */
                ev.id.c[4] = '1' + channel;
        }
-        ev.flags = 0;

        wrtd_log(WRTD_LOG_MSG_EV_GENERATED,
                 WRTD_LOG_GENERATED_DEVICE + (channel * 8), &ev, NULL);