update scb and backplane to v1.2.

a7d2c9b0 · hongming · bb741616 · a7d2c9b0 · a7d2c9b0 · bb741616
Commit a7d2c9b0 authored Sep 13, 2018 by hongming
155 changed files
--- a/.gitignore
+++ b/.gitignore
@@ -3,4 +3,6 @@
 Project output *
 *.htm
 Manufacture
+*.zip
+*.tar

--- a/doc/wrs-backplane-18sfp.pdf
+++ b/doc/wrs-backplane-18sfp.pdf
--- a/doc/wrs-fl-hw_v1.1.pdf
+++ b/doc/wrs-fl-hw_v1.1.pdf
--- a/wrs-backplane-18sfp/wrs-backplane-18sfp_V1.1.zip
+++ b/wrs-backplane-18sfp/wrs-backplane-18sfp_V1.1.zip
--- a/wrs-backplane-18sfp/pcb/wrs-backplane-18sfp.PcbDoc
+++ b/wrs-backplane-18sfp/pcb/wrs-backplane-18sfp.PcbDoc
--- a/wrs-backplane-18sfp/project/wrs-backplane-18sfp.PrjPCB
+++ b/wrs-backplane-18sfp/project/wrs-backplane-18sfp.PrjPCB
--- a/wrs-backplane-18sfp/project/wrs-backplane-18sfp.PrjPCBStructure
+++ b/wrs-backplane-18sfp/project/wrs-backplane-18sfp.PrjPCBStructure
--- a/wrs-backplane-18sfp/schematics/wrs_backplane_18SFP.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_backplane_18SFP.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_connector.Harness
+++ b/wrs-backplane-18sfp/schematics/wrs_connector.Harness
--- a/wrs-backplane-18sfp/schematics/wrs_connector.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_connector.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_i2c_mux.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_i2c_mux.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_link.Harness
+++ b/wrs-backplane-18sfp/schematics/wrs_link.Harness
--- a/wrs-backplane-18sfp/schematics/wrs_link.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_link.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_misc.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_misc.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_npth_mark_logo.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_npth_mark_logo.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_power.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_power.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_usb_dbg.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_usb_dbg.SchDoc
--- a/wrs-backplane-18sfp/schematics/wrs_usb_to_sfp.SchDoc
+++ b/wrs-backplane-18sfp/schematics/wrs_usb_to_sfp.SchDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2.rar
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2.rar
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/BACKPLANE.PrjPCB
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/BACKPLANE.PrjPCB
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/BACKPLANE.PrjPCBStructure
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/BACKPLANE.PrjPCBStructure
+Record=TopLevelDocument|FileName=BACKPLANE.SchDoc
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_CONNECTOR|SchDesignator=U_CONNECTOR|FileName=CONNECTOR.SchDoc|SymbolType=Normal|RawFileName=CONNECTOR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_I2C_MUX|SchDesignator=U_I2C_MUX|FileName=I2C_MUX.SchDoc|SymbolType=Normal|RawFileName=I2C_MUX.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_MISC|SchDesignator=U_MISC|FileName=MISC.SchDoc|SymbolType=Normal|RawFileName=MISC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_NPTH_MARK_LOGO|SchDesignator=U_NPTH_MARK_LOGO|FileName=NPTH_MARK_LOGO.SchDoc|SymbolType=Normal|RawFileName=NPTH_MARK_LOGO.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_POWER|SchDesignator=U_POWER|FileName=POWER.SchDoc|SymbolType=Normal|RawFileName=POWER.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_USB_TO_SFP|SchDesignator=U_USB_TO_SFP|FileName=USB_TO_SFP.SchDoc|SymbolType=Normal|RawFileName=USB_TO_SFP.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_1|SchDesignator=U_WR_LINK_1|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_2|SchDesignator=U_WR_LINK_2|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_3|SchDesignator=U_WR_LINK_3|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_4|SchDesignator=U_WR_LINK_4|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_5|SchDesignator=U_WR_LINK_5|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_6|SchDesignator=U_WR_LINK_6|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_7|SchDesignator=U_WR_LINK_7|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_8|SchDesignator=U_WR_LINK_8|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_9|SchDesignator=U_WR_LINK_9|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
--- a/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.0.PcbDoc
+++ b/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.0.PcbDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/BACKPLANE.PrjPCBStructure
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/BACKPLANE.PrjPCBStructure
+Record=TopLevelDocument|FileName=BACKPLANE.SchDoc
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_CONNECTOR|SchDesignator=U_CONNECTOR|FileName=CONNECTOR.SchDoc|SymbolType=Normal|RawFileName=CONNECTOR.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_I2C_MUX|SchDesignator=U_I2C_MUX|FileName=I2C_MUX.SchDoc|SymbolType=Normal|RawFileName=I2C_MUX.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_MISC|SchDesignator=U_MISC|FileName=MISC.SchDoc|SymbolType=Normal|RawFileName=MISC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_NPTH_MARK_LOGO|SchDesignator=U_NPTH_MARK_LOGO|FileName=NPTH_MARK_LOGO.SchDoc|SymbolType=Normal|RawFileName=NPTH_MARK_LOGO.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_POWER|SchDesignator=U_POWER|FileName=POWER.SchDoc|SymbolType=Normal|RawFileName=POWER.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_USB_TO_SFP|SchDesignator=U_USB_TO_SFP|FileName=USB_TO_SFP.SchDoc|SymbolType=Normal|RawFileName=USB_TO_SFP.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_1|SchDesignator=U_WR_LINK_1|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_2|SchDesignator=U_WR_LINK_2|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_3|SchDesignator=U_WR_LINK_3|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_4|SchDesignator=U_WR_LINK_4|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_5|SchDesignator=U_WR_LINK_5|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_6|SchDesignator=U_WR_LINK_6|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_7|SchDesignator=U_WR_LINK_7|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_8|SchDesignator=U_WR_LINK_8|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|SourceDocument=BACKPLANE.SchDoc|Designator=U_WR_LINK_9|SchDesignator=U_WR_LINK_9|FileName=WR_LINK.SchDoc|SymbolType=Normal|RawFileName=WR_LINK.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/BACKPLANE.SchDoc
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/BACKPLANE.SchDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/CONNECTOR.Harness
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/CONNECTOR.Harness
+WR_LINK_GTX=WR_LINK_RD_OUT_P,WR_LINK_RD_OUT_N,WR_LINK_TD_IN_P,WR_LINK_TD_IN_N
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/CONNECTOR.SchDoc
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/CONNECTOR.SchDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/Connector_GTX.Harness
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/Connector_GTX.Harness
+WR_LINK_GTX=WR_LINK_RD_OUT_P,WR_LINK_RD_OUT_N,WR_LINK_TD_IN_P,WR_LINK_TD_IN_N
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/I2C_MUX.SchDoc
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/I2C_MUX.SchDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/MISC.SchDoc
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/MISC.SchDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/NPTH_MARK_LOGO.SchDoc
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/NPTH_MARK_LOGO.SchDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/POWER.SchDoc
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/POWER.SchDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/SFP.Harness
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/SFP.Harness
+SFP_Control=SFP_TX_DISABLE,SFP_LOS,SFP_DETECT,SFP_SCL,SFP_SDA,SFP_TX_FAULT
+SFP_GTX=SFP_TD_IN_N,SFP_TD_IN_P,SFP_RD_OUT_N,SFP_RD_OUT_P
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/USB_TO_SFP.SchDoc
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/USB_TO_SFP.SchDoc
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/WR_LINK.Harness
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/WR_LINK.Harness
+WR_LINK_GTX=WR_LINK_TD_IN_N,WR_LINK_TD_IN_P,WR_LINK_RD_OUT_N,WR_LINK_RD_OUT_P
--- a/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/WR_LINK.SchDoc
+++ b/wrs-fl-backplane/wrs-fl-backplane-v1.2/Schematics/WR_LINK.SchDoc
--- a/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.1.PcbLib
+++ b/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.1.PcbLib
--- a/wrs-fl-hw/PCB-layout/AdditionCard.PcbDoc
+++ b/wrs-fl-hw/PCB-layout/AdditionCard.PcbDoc
--- a/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.1.PcbDoc
+++ b/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.1.PcbDoc
--- a/wrs-fl-hw/Schematics/CDCM61002.SchDoc
+++ b/wrs-fl-hw/Schematics/CDCM61002.SchDoc
--- a/wrs-fl-hw/Schematics/CLK_25M_DMTD.Harness
+++ b/wrs-fl-hw/Schematics/CLK_25M_DMTD.Harness
--- a/wrs-fl-hw/Schematics/CLK_25M_DMTD.SchDoc
+++ b/wrs-fl-hw/Schematics/CLK_25M_DMTD.SchDoc
--- a/wrs-fl-hw/Schematics/CLK_25M_FPGA.SchDoc
+++ b/wrs-fl-hw/Schematics/CLK_25M_FPGA.SchDoc
--- a/wrs-fl-hw/Schematics/CLK_25M_GTX.Harness
+++ b/wrs-fl-hw/Schematics/CLK_25M_GTX.Harness
--- a/wrs-fl-hw/Schematics/CLK_25M_GTX.SchDoc
+++ b/wrs-fl-hw/Schematics/CLK_25M_GTX.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_100M_Ethernet.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_100M_Ethernet.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_DDR2.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_DDR2.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_EBI1_FPGA_Memory.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_EBI1_FPGA_Memory.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_IO_Ports.Harness
+++ b/wrs-fl-hw/Schematics/CPU_IO_Ports.Harness
--- a/wrs-fl-hw/Schematics/CPU_IO_Ports.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_IO_Ports.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_JTAG.Harness
+++ b/wrs-fl-hw/Schematics/CPU_JTAG.Harness
--- a/wrs-fl-hw/Schematics/CPU_JTAG.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_JTAG.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_POWER.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_POWER.SchDoc
--- a/wrs-fl-hw/Schematics/CPU_USB.SchDoc
+++ b/wrs-fl-hw/Schematics/CPU_USB.SchDoc
--- a/wrs-fl-hw/Schematics/Connectors.Harness
+++ b/wrs-fl-hw/Schematics/Connectors.Harness
--- a/wrs-fl-hw/Schematics/Connectors.SchDoc
+++ b/wrs-fl-hw/Schematics/Connectors.SchDoc
--- a/wrs-fl-hw/Schematics/DCDC.SchDoc
+++ b/wrs-fl-hw/Schematics/DCDC.SchDoc
--- a/wrs-fl-hw/Schematics/DCDC_ALL.SchDoc
+++ b/wrs-fl-hw/Schematics/DCDC_ALL.SchDoc
--- a/wrs-fl-hw/Schematics/DFF_SYNC.SchDoc
+++ b/wrs-fl-hw/Schematics/DFF_SYNC.SchDoc
--- a/wrs-fl-hw/Schematics/EXT_10M_IN.SchDoc
+++ b/wrs-fl-hw/Schematics/EXT_10M_IN.SchDoc
--- a/wrs-fl-hw/Schematics/EXT_PLL.Harness
+++ b/wrs-fl-hw/Schematics/EXT_PLL.Harness
--- a/wrs-fl-hw/Schematics/EXT_PLL.SchDoc
+++ b/wrs-fl-hw/Schematics/EXT_PLL.SchDoc
--- a/wrs-fl-hw/Schematics/EXT_PLL_POWER.SchDoc
+++ b/wrs-fl-hw/Schematics/EXT_PLL_POWER.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_Configuration.Harness
+++ b/wrs-fl-hw/Schematics/FPGA_Configuration.Harness
--- a/wrs-fl-hw/Schematics/FPGA_Configuration.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_Configuration.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_EXT_PLL.Harness
+++ b/wrs-fl-hw/Schematics/FPGA_EXT_PLL.Harness
--- a/wrs-fl-hw/Schematics/FPGA_EXT_PLL.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_EXT_PLL.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_GPIOs.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_GPIOs.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_GTX.Harness
+++ b/wrs-fl-hw/Schematics/FPGA_GTX.Harness
--- a/wrs-fl-hw/Schematics/FPGA_GTX.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_GTX.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_POWER_DGND.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_POWER_DGND.SchDoc
--- a/wrs-fl-hw/Schematics/FPGA_Peripherals_Control.Harness
+++ b/wrs-fl-hw/Schematics/FPGA_Peripherals_Control.Harness
--- a/wrs-fl-hw/Schematics/FPGA_Peripherals_Control.SchDoc
+++ b/wrs-fl-hw/Schematics/FPGA_Peripherals_Control.SchDoc
--- a/wrs-fl-hw/Schematics/HeatSink.SchDoc
+++ b/wrs-fl-hw/Schematics/HeatSink.SchDoc
--- a/wrs-fl-hw/Schematics/LDO.SchDoc
+++ b/wrs-fl-hw/Schematics/LDO.SchDoc
--- a/wrs-fl-hw/Schematics/LDO_ALL.Harness
+++ b/wrs-fl-hw/Schematics/LDO_ALL.Harness
--- a/wrs-fl-hw/Schematics/LDO_ALL.SchDoc
+++ b/wrs-fl-hw/Schematics/LDO_ALL.SchDoc
--- a/wrs-fl-hw/Schematics/LDO_XO.SchDoc
+++ b/wrs-fl-hw/Schematics/LDO_XO.SchDoc
--- a/wrs-fl-hw/Schematics/LVPECL_FANOUT.Harness
+++ b/wrs-fl-hw/Schematics/LVPECL_FANOUT.Harness
--- a/wrs-fl-hw/Schematics/LVPECL_FANOUT.SchDoc
+++ b/wrs-fl-hw/Schematics/LVPECL_FANOUT.SchDoc
--- a/wrs-fl-hw/Schematics/NPTH_MARK_LOGO.SchDoc
+++ b/wrs-fl-hw/Schematics/NPTH_MARK_LOGO.SchDoc
--- a/wrs-fl-hw/Schematics/PLL.Harness
+++ b/wrs-fl-hw/Schematics/PLL.Harness
--- a/wrs-fl-hw/Schematics/PLL.SchDoc
+++ b/wrs-fl-hw/Schematics/PLL.SchDoc
--- a/wrs-fl-hw/Schematics/PLL_POWER.SchDoc
+++ b/wrs-fl-hw/Schematics/PLL_POWER.SchDoc
--- a/wrs-fl-hw/Schematics/PPS.SchDoc
+++ b/wrs-fl-hw/Schematics/PPS.SchDoc
--- a/wrs-fl-hw/Schematics/RS232.Harness
+++ b/wrs-fl-hw/Schematics/RS232.Harness
--- a/wrs-fl-hw/Schematics/RS232.SchDoc
+++ b/wrs-fl-hw/Schematics/RS232.SchDoc
--- a/wrs-fl-hw/Schematics/SCB_MAIN.SchDoc
+++ b/wrs-fl-hw/Schematics/SCB_MAIN.SchDoc
--- a/wrs-fl-hw/Schematics/SENSOR.SchDoc
+++ b/wrs-fl-hw/Schematics/SENSOR.SchDoc
--- a/wrs-fl-hw/Schematics/UART_TO_USB.Harness
+++ b/wrs-fl-hw/Schematics/UART_TO_USB.Harness
--- a/wrs-fl-hw/Schematics/UART_TO_USB.SchDoc
+++ b/wrs-fl-hw/Schematics/UART_TO_USB.SchDoc
--- a/wrs-fl-hw/Schematics/V_REF.SchDoc
+++ b/wrs-fl-hw/Schematics/V_REF.SchDoc
--- a/wrs-fl-hw/Schematics/WDT_ARM.SchDoc
+++ b/wrs-fl-hw/Schematics/WDT_ARM.SchDoc
--- a/wrs-fl-hw/Schematics/WDT_FPGA.Harness
+++ b/wrs-fl-hw/Schematics/WDT_FPGA.Harness
--- a/wrs-fl-hw/Schematics/WDT_FPGA.SchDoc
+++ b/wrs-fl-hw/Schematics/WDT_FPGA.SchDoc
--- a/wrs-fl-hw/wrs-fl-hw.PrjPCB
+++ b/wrs-fl-hw/wrs-fl-hw.PrjPCB
--- a/wrs-fl-scb/wrs-fl-scb-v1.1/wrs-fl-hw.PrjPCBStructure
+++ b/wrs-fl-scb/wrs-fl-scb-v1.1/wrs-fl-hw.PrjPCBStructure
--- a/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.2.PcbDoc
+++ b/wrs-fl-hw/PCB-layout/wrs-fl-hw_v1.2.PcbDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CDCM61002.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CDCM61002.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_DMTD.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_DMTD.Harness
+DAC_CONTROL=DAC_DIN,DAC_SYNC,DAC_SCLK
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_DMTD.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_DMTD.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_FPGA.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_FPGA.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_GTX.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_GTX.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_GTX.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CLK_25M_GTX.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_100M_Ethernet.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_100M_Ethernet.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_DDR2.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_DDR2.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_EBI1_FPGA_Memory.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_EBI1_FPGA_Memory.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_IO_Ports.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_IO_Ports.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_IO_Ports.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_IO_Ports.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_JTAG.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_JTAG.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_JTAG.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_JTAG.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_POWER.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_POWER.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_USB.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/CPU_USB.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/Connectors.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/Connectors.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/Connectors.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/Connectors.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/DCDC.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/DCDC.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/DCDC_ALL.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/DCDC_ALL.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/DFF_SYNC.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/DFF_SYNC.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/EXT_10M_IN.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/EXT_10M_IN.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/EXT_PLL.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/EXT_PLL.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/EXT_PLL.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/EXT_PLL.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/EXT_PLL_POWER.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/EXT_PLL_POWER.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_Configuration.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_Configuration.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_Configuration.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_Configuration.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_EXT_PLL.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_EXT_PLL.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_EXT_PLL.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_EXT_PLL.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_GPIOs.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_GPIOs.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_GTX.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_GTX.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_GTX.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_GTX.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_POWER_DGND.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_POWER_DGND.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_Peripherals_Control.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_Peripherals_Control.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_Peripherals_Control.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/FPGA_Peripherals_Control.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/HeatSink.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/HeatSink.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LDO.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LDO.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LDO_ALL.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LDO_ALL.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LDO_ALL.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LDO_ALL.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LDO_XO.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LDO_XO.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LVPECL_FANOUT.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LVPECL_FANOUT.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LVPECL_FANOUT.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/LVPECL_FANOUT.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/NPTH_MARK_LOGO.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/NPTH_MARK_LOGO.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/PLL.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/PLL.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/PLL.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/PLL.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/PLL_POWER.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/PLL_POWER.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/PPS.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/PPS.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/RS232.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/RS232.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/RS232.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/RS232.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/SCB_MAIN.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/SCB_MAIN.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/SENSOR.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/SENSOR.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/UART_TO_USB.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/UART_TO_USB.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/UART_TO_USB.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/UART_TO_USB.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/V_REF.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/V_REF.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/WDT_ARM.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/WDT_ARM.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/WDT_FPGA.Harness
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/WDT_FPGA.Harness
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/WDT_FPGA.SchDoc
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/Schematics/WDT_FPGA.SchDoc
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/wrs-fl-scb-v1.2.PrjPCB
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/wrs-fl-scb-v1.2.PrjPCB
--- a/wrs-fl-scb/wrs-fl-scb-v1.2/wrs-fl-scb-v1.2.PrjPCBStructure
+++ b/wrs-fl-scb/wrs-fl-scb-v1.2/wrs-fl-scb-v1.2.PrjPCBStructure