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WRS Fan-less hardware
Commit 4e44ce09 authored by hongming's avatar hongming
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V1.0. Ready for review.

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PCB-layout/wrs-fl-hw_v1.0.PcbDoc.htm 0 → 100644
View file @ 4e44ce09
<html>
<head>
<META http-equiv="Content-Type" content="text/html">
<style type="text/css">
h1, h2, h3, h4, h5, h6 {
font-family : 'segoe-ui',arial,sans-serif;
font-size:15pt;
font-weight:normal;
line-height:40px;
color : #000;
background-color : #dedede;
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font-family : verdana;
background: #f1f1f1;
font-size:13px;
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td, th {
padding: 0.5em;
text-align : left;
width: auto;
border:1px solid #DEDEDE;
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th {
background-color : #DEDEDE;
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th.column1, td.column1 {
text-align: left;
width : 18%;
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table {
width : 100%;
border-collapse: collapse;
font-size:13px;
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.front_matter, .front_matter_column1, .front_matter_column2, .front_matter_column3 {
padding-top : 0.1em;
padding-bottom : 0.1em;
border : 0px solid black;
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vertical-align: top
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.front_matter_column1 {
text-align : right;
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.total_column1, .total_column {
font-weight : bold;
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.total_column1 {
text-align : right;
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.front_matter_column2 {
text-align : center;
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.front_matter_column3 {
text-align : left;
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.warning, .error {
color : red;
font-weight : bold;
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/*background-color : #EEEEE0 */
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/*background-color : #F3F3E3 */
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tr.onmouseover_odd, tr.onmouseover_even {
background-color : #FFF;
}
a:link, a:visited, .q a:link,.q a:active,.q {
color: #21489e;
}
a:link.callback, a:visited.callback {
color: #008000
}
a:link.customize, a:visited.customize {
position: absolute;
right: 16px; top: 30px;
font-family:'segoe ui',arial,tahoma,sans-serif;
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left : 20px;
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HR{
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table,th,td,hr{
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</style>
</head>
<body>
<a href="dxpprocess://Client:SetupPreferences?Server=PCB|PageName=General" class="customize"><acronym title="dxpprocess://Client:SetupPreferences?Server=PCB|PageName=General">Reporting Options</acronym></a>
<h1>File in Previous Format</h1>
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3">2018-3-6</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3">23:40:37</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3"><a href="file://D:\PCB_Collection\024wr-switch-hw\ohwr\\PCB-layout\wrs-fl-hw_v1.0.PcbDoc" class="file"><acronym title="D:\PCB_Collection\024wr-switch-hw\ohwr\\PCB-layout\wrs-fl-hw_v1.0.PcbDoc">D:\PCB_Collection\024wr-switch-hw\ohwr\\PCB-layout\wrs-fl-hw_v1.0.PcbDoc</acronym></a></td>
</tr>
</table>
<br>
<table>
<tr>
<th style="text-align : left" colspan="1" class="">Version</th>
<th style="text-align : left" colspan="1" class="">Warning</th>
</tr>
</table>
<br><hr>
<p>This file was generated by <b>an earlier</b> version of the software</p>
</body>
</html>
Schematics/CLK_25M_DMTD.Harness 0 → 100644
View file @ 4e44ce09
DAC_CONTROL=DAC_DMTD_DIN,DAC_DMTD_SYNC,DAC_DMTD_SCLK
Schematics/CPU_100M_Ethernet.Harness 0 → 100644
View file @ 4e44ce09
ETH_100MHz=TXD0,TXD1,RXD0,RXD1,TX_EN,CRS_DV,TX_CLK,MDIO,MDC,NRST,RX_ER
Schematics/CPU_IO_Ports.Harness 0 → 100644
View file @ 4e44ce09
CPU_SSC=RF1,RK1,RD1,TD1,TK1,TF1
SPI1=SPI1_NPCS0,SPI1_SPCK,SPI1_MOSI,SPI1_MISO
Schematics/CPU_JTAG.Harness 0 → 100644
View file @ 4e44ce09
CPU_JTAG=JNRST,JTDO,JRTCK,JTCK,JTMS,JTDI,JNTRST
Schematics/Connectors.Harness 0 → 100644
View file @ 4e44ce09
CPU_JTAG=JNTRST,JTDI,JTMS,JTCK,JRTCK,JTDO,JNRST
CPU_SSC=TF1,TK1,TD1,RD1,RK1,RF1
ETH_100MHz=TXD0,TXD1,RXD0,RXD1,TX_EN,CRS_DV,TX_CLK,MDIO,MDC,NRST,RX_ER
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDO,FPGA_TDI
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_N,MGTTX112_0_P,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RXD,RS232_FPGA_TXD,RS232_FPGA_RXD
uTCA_CLK=MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N
Schematics/EXT_PLL.Harness 0 → 100644
View file @ 4e44ce09
EXT_PLL_CTRL=EXT_PLL_SYNC,EXT_PLL_SDI,EXT_PLL_SDO,EXT_PLL_SCLK,EXT_PLL_REFSEL,EXT_PLL_RESET,EXT_PLL_LOCK,EXT_PLL_STAT,EXT_PLL_CS
Schematics/FPGA_Configuration.Harness 0 → 100644
View file @ 4e44ce09
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO
FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
PLL_CLKS=REF_CLK_P,REF_CLK_N,AUX_CLK_P,AUX_CLK_N
Schematics/FPGA_EXT_PLL.Harness 0 → 100644
View file @ 4e44ce09
EXT_PLL_CTRL=EXT_PLL_SYNC,EXT_PLL_SDI,EXT_PLL_SDO,EXT_PLL_SCLK,EXT_PLL_REFSEL,EXT_PLL_RESET,EXT_PLL_LOCK,EXT_PLL_STAT,EXT_PLL_CS
Schematics/FPGA_GTX.Harness 0 → 100644
View file @ 4e44ce09
MGTREFCLK=MGTREFCLK112_P,MGTREFCLK112_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK116_P,MGTREFCLK116_N
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_P,MGTTX112_0_N,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
Schematics/FPGA_Peripherals_Control.Harness 0 → 100644
View file @ 4e44ce09
DAC_CONTROL=DAC_DMTD_DIN,DAC_DMTD_SYNC,DAC_DMTD_SCLK
PLL_CONTROL=PLL_CS,PLL_STAT,PLL_LOCK,PLL_RESET,PLL_REFSEL,PLL_SCLK,PLL_SDO,PLL_SDI,PLL_SYNC
Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
Schematics/LDO_ALL.Harness 0 → 100644
View file @ 4e44ce09
Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG
Schematics/LVPECL_FANOUT.Harness 0 → 100644
View file @ 4e44ce09
MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
Schematics/PLL.Harness 0 → 100644
View file @ 4e44ce09
PLL_CLKS=REF_CLK_P,REF_CLK_N,AUX_CLK_P,AUX_CLK_N
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS
uTCA_CLK=MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N
Schematics/RS232.Harness 0 → 100644
View file @ 4e44ce09
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RXD,RS232_FPGA_TXD,RS232_FPGA_RXD
Schematics/Todo.txt 0 → 100644
View file @ 4e44ce09
Todo:
Tear Drop
Check PG signals ofall LDOs
Schematics/WDT_FPGA.Harness 0 → 100644
View file @ 4e44ce09
FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
wrs-fl-hw_v1.0.PrjPCB 0 → 100644
View file @ 4e44ce09
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wrs-fl-hw_v1.0.PrjPCBStructure 0 → 100644
View file @ 4e44ce09
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