softpll: don't set Main DAC register to 0 during initialization - can break the link on fast tuning oscillators (i.e. Si57x).

Longer explanation: too abrupt frequency changes cause digitally controlled oscillators to either produce glitches in its output or just cause it to detune too fast
(in the case of Si57x, 100 ppm over 10 us). If such an oscillator is used to drive FPGA's transceivers (or other PLLs), they may lose lock (and hence, a PHY referenced
to such clock may lose link).