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Software for White Rabbit PTP Core
Commit e98a0cf1 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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dev/endpoint: initial support for multiple endpoint devices

parent 3abe33fa
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Showing with 217 additions and 175 deletions
dev/endpoint.c
View file @ e98a0cf1
......@@ -23,171 +23,160 @@
from the serdes bitslip value */
#define PICOS_PER_SERIAL_BIT 800
/* Number of raw phase samples averaged by the DMTD detector in the Endpoint during single phase measurement.
The bigger, the better precision, but slower rate */
#define DMTD_AVG_SAMPLES 256
static int autoneg_enabled;
volatile struct EP_WB *EP;
/* functions for accessing PCS (MDIO) registers */
uint16_t ep_pcs_read(int location)
uint16_t ep_pcs_read(struct wr_endpoint_device *dev, int location)
{
EP->MDIO_CR = EP_MDIO_CR_ADDR_W(location >> 2);
while ((EP->MDIO_ASR & EP_MDIO_ASR_READY) == 0) ;
return EP_MDIO_ASR_RDATA_R(EP->MDIO_ASR) & 0xffff;
ep_write( dev, EP_REG_MDIO_CR, EP_MDIO_CR_ADDR_W(location >> 2) );
while (( ep_read(dev, EP_REG_MDIO_ASR) & EP_MDIO_ASR_READY) == 0) ;
return EP_MDIO_ASR_RDATA_R(ep_read(dev, EP_REG_MDIO_ASR)) & 0xffff;
}
void ep_pcs_write(int location, int value)
void ep_pcs_write(struct wr_endpoint_device *dev, int location, int value)
{
EP->MDIO_CR = EP_MDIO_CR_ADDR_W(location >> 2)
ep_write(dev, EP_REG_MDIO_CR, EP_MDIO_CR_ADDR_W(location >> 2)
| EP_MDIO_CR_DATA_W(value)
| EP_MDIO_CR_RW;
| EP_MDIO_CR_RW );
while ((EP->MDIO_ASR & EP_MDIO_ASR_READY) == 0) ;
while (( ep_read(dev, EP_REG_MDIO_ASR) & EP_MDIO_ASR_READY) == 0) ;
}
void ep_get_mac_addr(uint8_t *dev_addr)
void ep_get_mac_addr(struct wr_endpoint_device *dev, uint8_t *dev_addr)
{
dev_addr[5] = (EP->MACL & 0x000000ff);
dev_addr[4] = (EP->MACL & 0x0000ff00) >> 8;
dev_addr[3] = (EP->MACL & 0x00ff0000) >> 16;
dev_addr[2] = (EP->MACL & 0xff000000) >> 24;
dev_addr[1] = (EP->MACH & 0x000000ff);
dev_addr[0] = (EP->MACH & 0x0000ff00) >> 8;
uint32_t macl = ep_read(dev, EP_REG_MACL);
uint32_t mach = ep_read(dev, EP_REG_MACH);
dev_addr[5] = (macl & 0x000000ff);
dev_addr[4] = (macl & 0x0000ff00) >> 8;
dev_addr[3] = (macl & 0x00ff0000) >> 16;
dev_addr[2] = (macl & 0xff000000) >> 24;
dev_addr[1] = (mach & 0x000000ff);
dev_addr[0] = (mach & 0x0000ff00) >> 8;
}
static uint8_t ep_mac_addr[6];
static int is_mac_addr_set = 0;
void ep_set_mac_addr(uint8_t *addr)
void ep_set_mac_addr(struct wr_endpoint_device* dev, uint8_t *addr)
{
EP = (volatile struct EP_WB *)BASE_EP;
memcpy(ep_mac_addr, addr, 6);
memcpy(dev->mac_addr, addr, 6);
EP->MACL = ((uint32_t) ep_mac_addr[2] << 24)
| ((uint32_t) ep_mac_addr[3] << 16)
| ((uint32_t) ep_mac_addr[4] << 8)
| ((uint32_t) ep_mac_addr[5]);
ep_write(dev, EP_REG_MACL, ((uint32_t) dev->mac_addr[2] << 24)
| ((uint32_t) dev->mac_addr[3] << 16)
| ((uint32_t) dev->mac_addr[4] << 8)
| ((uint32_t) dev->mac_addr[5]) );
EP->MACH = ((uint32_t) ep_mac_addr[0] << 8)
| ((uint32_t) ep_mac_addr[1]);
ep_write(dev, EP_REG_MACH, ((uint32_t) dev->mac_addr[0] << 8)
| ((uint32_t) dev->mac_addr[1]) );
is_mac_addr_set = 1;
dev->flags |= EP_DEV_MAC_ADDR_SET;
}
int ep_is_mac_addr_set()
int ep_is_mac_addr_set(struct wr_endpoint_device* dev)
{
return is_mac_addr_set;
return (dev->flags & EP_DEV_MAC_ADDR_SET) ? 1 : 0;
}
/* Initializes the endpoint and sets its local MAC address */
void ep_init()
void ep_init(struct wr_endpoint_device* dev, void *base_addr)
{
EP = (volatile struct EP_WB *)BASE_EP;
dev->base = base_addr;
dev->flags = 0;
EP->MACL = ((uint32_t) ep_mac_addr[2] << 24)
| ((uint32_t) ep_mac_addr[3] << 16)
| ((uint32_t) ep_mac_addr[4] << 8)
| ((uint32_t) ep_mac_addr[5]);
EP->MACH = ((uint32_t) ep_mac_addr[0] << 8)
| ((uint32_t) ep_mac_addr[1]);
ep_sfp_enable(1);
ep_sfp_enable(dev, 1);
#if 0
if (!IS_WR_NODE_SIM){
*(unsigned int *)(0x62000) = 0x2; // reset network stuff (cleanup required!)
*(unsigned int *)(0x62000) = 0;
}
#endif
EP->ECR = 0; /* disable Endpoint */
EP->VCR0 = EP_VCR0_QMODE_W(3); /* disable VLAN unit - not used by WRPC */
EP->RFCR = EP_RFCR_MRU_W(1518); /* Set the max RX packet size */
EP->TSCR = EP_TSCR_EN_TXTS | EP_TSCR_EN_RXTS; /* Enable timestamping */
/* Configure DMTD phase tracking */
EP->DMCR = EP_DMCR_EN | EP_DMCR_N_AVG_W(DMTD_AVG_SAMPLES);
ep_write(dev, EP_REG_ECR, 0); /* disable Endpoint */
ep_write(dev, EP_REG_VCR0, EP_VCR0_QMODE_W(3)); /* disable VLAN unit - not used by WRPC */
ep_write(dev, EP_REG_RFCR, EP_RFCR_MRU_W(1518)); /* Set the max RX packet size */
ep_write(dev, EP_REG_TSCR, EP_TSCR_EN_TXTS | EP_TSCR_EN_RXTS); /* Enable timestamping */
}
void ep_reset_phy(void)
void ep_reset_phy(struct wr_endpoint_device* dev)
{
uint32_t mcr;
/* Reset the GTP Transceiver - it's important to do the GTP phase alignment every time
we start up the software, otherwise the calibration RX/TX deltas may not be correct */
ep_pcs_write(MDIO_REG_MCR, MDIO_MCR_PDOWN); /* reset the PHY */
ep_pcs_write(dev, MDIO_REG_MCR, MDIO_MCR_PDOWN); /* reset the PHY */
if (!IS_WR_NODE_SIM)
timer_delay_ms(200);
ep_pcs_write(MDIO_REG_MCR, MDIO_MCR_RESET); /* reset the PHY */
ep_pcs_write(MDIO_REG_MCR, 0); /* reset the PHY */
ep_pcs_write(dev, MDIO_REG_MCR, MDIO_MCR_RESET); /* reset the PHY */
ep_pcs_write(dev, MDIO_REG_MCR, 0); /* reset the PHY */
/* Don't advertise anything - we don't want flow control */
ep_pcs_write(MDIO_REG_ADVERTISE, 0);
ep_pcs_write(dev, MDIO_REG_ADVERTISE, 0);
mcr = MDIO_MCR_SPEED1000_MASK | MDIO_MCR_FULLDPLX_MASK;
if (autoneg_enabled)
if (dev->flags & EP_DEV_AUTONEG_ENABLED)
mcr |= MDIO_MCR_ANENABLE | MDIO_MCR_ANRESTART;
ep_pcs_write(MDIO_REG_MCR, mcr);
ep_pcs_write(dev, MDIO_REG_MCR, mcr);
}
/* Enables/disables transmission and reception. When autoneg is set to 1,
starts up 802.3 autonegotiation process */
int ep_enable(int enabled, int autoneg)
int ep_enable(struct wr_endpoint_device* dev, int enabled, int autoneg)
{
if (!enabled) {
EP->ECR = 0;
ep_write(dev, EP_REG_ECR, 0);
return 0;
}
/* Disable the endpoint */
EP->ECR = 0;
ep_write(dev, EP_REG_ECR, 0);
if (!IS_WR_NODE_SIM)
mac_dbg("MAC/Endpoint ID: %x\n", EP->IDCODE);
mac_dbg("MAC/Endpoint ID: %x\n", ep_read(dev, EP_REG_IDCODE) );
/* Load default packet classifier rules - see ep_pfilter.c for details */
pfilter_init_default();
ep_pfilter_init_default( dev );
/* Enable TX/RX paths, reset RMON counters */
EP->ECR = EP_ECR_TX_EN | EP_ECR_RX_EN | EP_ECR_RST_CNT;
ep_write(dev, EP_REG_ECR, EP_ECR_TX_EN | EP_ECR_RX_EN | EP_ECR_RST_CNT );
autoneg_enabled = autoneg;
if(autoneg)
dev->flags |= EP_DEV_AUTONEG_ENABLED;
else
dev->flags &= ~EP_DEV_AUTONEG_ENABLED;
ep_reset_phy();
ep_reset_phy(dev);
return 0;
}
/* Checks the link status. If the link is up, returns non-zero
and stores the Link Partner Ability (LPA) autonegotiation register at *lpa */
int ep_link_up(uint16_t * lpa)
int ep_link_up(struct wr_endpoint_device* dev, uint16_t * lpa)
{
uint16_t flags = MDIO_MSR_LSTATUS;
volatile uint16_t msr;
if (autoneg_enabled)
if (dev->flags & EP_DEV_AUTONEG_ENABLED)
flags |= MDIO_MSR_ANEGCOMPLETE;
msr = ep_pcs_read(MDIO_REG_MSR);
msr = ep_pcs_read(MDIO_REG_MSR); /* Read this flag twice to make sure the status is updated */
msr = ep_pcs_read(dev, MDIO_REG_MSR);
msr = ep_pcs_read(dev, MDIO_REG_MSR); /* Read this flag twice to make sure the status is updated */
if (lpa)
*lpa = ep_pcs_read(MDIO_REG_LPA);
*lpa = ep_pcs_read(dev, MDIO_REG_LPA);
return (msr & flags) == flags ? 1 : 0;
}
int ep_get_bitslide()
int ep_get_bitslide(struct wr_endpoint_device* dev)
{
return PICOS_PER_SERIAL_BIT *
MDIO_WR_SPEC_BSLIDE_R(ep_pcs_read(MDIO_REG_WR_SPEC));
MDIO_WR_SPEC_BSLIDE_R(ep_pcs_read(dev, MDIO_REG_WR_SPEC));
}
/* Returns the TX/RX latencies. They are valid only when the link is up. */
int ep_get_deltas(uint32_t * delta_tx, uint32_t * delta_rx)
int ep_get_deltas(struct wr_endpoint_device* dev, uint32_t * delta_tx, uint32_t * delta_rx)
{
/* fixme: these values should be stored in calibration block in the EEPROM on the FMC. Also, the TX/RX delays of a particular SFP
should be added here */
......@@ -195,47 +184,48 @@ int ep_get_deltas(uint32_t * delta_tx, uint32_t * delta_rx)
*delta_rx =
sfp_deltaRx +
PICOS_PER_SERIAL_BIT *
MDIO_WR_SPEC_BSLIDE_R(ep_pcs_read(MDIO_REG_WR_SPEC));
MDIO_WR_SPEC_BSLIDE_R(ep_pcs_read(dev, MDIO_REG_WR_SPEC));
return 0;
}
int ep_cal_pattern_enable()
int ep_cal_pattern_enable(struct wr_endpoint_device* dev)
{
uint32_t val;
val = ep_pcs_read(MDIO_REG_WR_SPEC);
val = ep_pcs_read(dev, MDIO_REG_WR_SPEC);
val |= MDIO_WR_SPEC_TX_CAL;
ep_pcs_write(MDIO_REG_WR_SPEC, val);
ep_pcs_write(dev, MDIO_REG_WR_SPEC, val);
return 0;
}
int ep_cal_pattern_disable()
int ep_cal_pattern_disable(struct wr_endpoint_device* dev)
{
uint32_t val;
val = ep_pcs_read(MDIO_REG_WR_SPEC);
val = ep_pcs_read(dev, MDIO_REG_WR_SPEC);
val &= (~MDIO_WR_SPEC_TX_CAL);
ep_pcs_write(MDIO_REG_WR_SPEC, val);
ep_pcs_write(dev, MDIO_REG_WR_SPEC, val);
return 0;
}
int ep_timestamper_cal_pulse()
int ep_timestamper_cal_pulse(struct wr_endpoint_device* dev)
{
//pp_printf("calPulse ep @ %p\n", EP);
EP->TSCR |= EP_TSCR_RX_CAL_START;
ep_write(dev, EP_REG_TSCR, ep_read(dev, EP_REG_TSCR) | EP_TSCR_RX_CAL_START );
timer_delay_ms(1);
return EP->TSCR & EP_TSCR_RX_CAL_RESULT ? 1 : 0;
return ep_read(dev, EP_REG_TSCR) & EP_TSCR_RX_CAL_RESULT ? 1 : 0;
}
int ep_sfp_enable(int ena)
int ep_sfp_enable(struct wr_endpoint_device* dev, int ena)
{
uint32_t val;
val = ep_pcs_read(MDIO_REG_ECTRL);
val = ep_pcs_read(dev, MDIO_REG_ECTRL);
if(ena)
val &= (~MDIO_ECTRL_SFP_TX_DISABLE);
else
val |= MDIO_ECTRL_SFP_TX_DISABLE;
ep_pcs_write(MDIO_REG_ECTRL, val);
ep_pcs_write(dev, MDIO_REG_ECTRL, val);
return 0;
}
dev/ep_pfilter.c
View file @ e98a0cf1
......@@ -44,9 +44,6 @@ struct rule_set {
}
};
extern volatile struct EP_WB *EP;
static uint32_t swap32(uint32_t v)
{
uint32_t res;
......@@ -58,7 +55,7 @@ static uint32_t swap32(uint32_t v)
return res;
}
void pfilter_init_default(void)
void ep_pfilter_init_default(struct wr_endpoint_device *dev)
{
struct rule_set *s;
uint8_t mac[6];
......@@ -112,7 +109,7 @@ void pfilter_init_default(void)
* Patch the local MAC address in place,
* in the first three instructions after NOP
*/
ep_get_mac_addr(mac);
ep_get_mac_addr(dev, mac);
v[2] &= ~(0xffff << 13);
v[4] &= ~(0xffff << 13);
v[6] &= ~(0xffff << 13);
......@@ -150,7 +147,7 @@ void pfilter_init_default(void)
}
}
EP->PFCR0 = 0; // disable pfilter
ep_write( dev, EP_REG_PFCR0, 0); // disable pfilter
for (i = 0, v = vini + 1; v < vend; v += 2, i++) {
uint32_t cr0, cr1;
......@@ -164,8 +161,8 @@ void pfilter_init_default(void)
cr0 = EP_PFCR0_MM_ADDR_W(i) | EP_PFCR0_MM_DATA_MSB_W(cmd_word >> 12) |
EP_PFCR0_MM_WRITE_MASK;
EP->PFCR1 = cr1;
EP->PFCR0 = cr0;
ep_write( dev, EP_REG_PFCR1, cr1 );
ep_write( dev, EP_REG_PFCR0, cr0 );
}
/* Restore the 0xaaa vlan number, so we can re-patch next time */
......@@ -184,5 +181,5 @@ void pfilter_init_default(void)
v[4] |= 0x5678 << 13;
v[6] |= 0x9abc << 13;
EP->PFCR0 = EP_PFCR0_ENABLE;
ep_write( dev, EP_REG_PFCR0, EP_PFCR0_ENABLE);
}
include/dev/endpoint.h
View file @ e98a0cf1
......@@ -6,6 +6,7 @@
#ifndef __ENDPOINT_H
#define __ENDPOINT_H
#include <hw/rawmem.h>
#include <stdint.h>
typedef enum {
......@@ -19,24 +20,43 @@ typedef enum {
NOT = 7
} pfilter_op_t;
void ep_init(void);
void ep_set_mac_addr(uint8_t *addr);
void ep_get_mac_addr(uint8_t *addr);
int ep_is_mac_addr_set(void);
int ep_enable(int enabled, int autoneg);
int ep_link_up(uint16_t * lpa);
int ep_get_bitslide(void);
int ep_get_deltas(uint32_t * delta_tx, uint32_t * delta_rx);
int ep_get_psval(int32_t * psval);
int ep_cal_pattern_enable(void);
int ep_cal_pattern_disable(void);
int ep_timestamper_cal_pulse(void);
int ep_sfp_enable(int ena);
uint16_t ep_pcs_read(int location);
void ep_pcs_write(int location, int value);
void ep_reset_phy(void);
void pfilter_init_default(void);
#define EP_DEV_MAC_ADDR_SET ( 1<<0 )
#define EP_DEV_AUTONEG_ENABLED ( 1<<1 )
struct wr_endpoint_device
{
uint8_t mac_addr[6];
int flags;
void *base;
};
static inline void ep_write( struct wr_endpoint_device* dev, uint32_t addr, uint32_t data)
{
writel( data, addr + dev->base );
}
static inline uint32_t ep_read( struct wr_endpoint_device* dev, uint32_t addr)
{
return readl( addr + dev->base );
}
void ep_init(struct wr_endpoint_device* dev, void *base_addr);
void ep_set_mac_addr(struct wr_endpoint_device* dev, uint8_t *addr);
void ep_get_mac_addr(struct wr_endpoint_device* dev,uint8_t *addr);
int ep_is_mac_addr_set(struct wr_endpoint_device* dev);
int ep_enable(struct wr_endpoint_device* dev, int enabled, int autoneg);
int ep_link_up(struct wr_endpoint_device* dev, uint16_t * lpa);
int ep_get_bitslide(struct wr_endpoint_device* dev);
int ep_get_deltas(struct wr_endpoint_device* dev,uint32_t * delta_tx, uint32_t * delta_rx);
int ep_cal_pattern_enable(struct wr_endpoint_device* dev);
int ep_cal_pattern_disable(struct wr_endpoint_device* dev);
int ep_timestamper_cal_pulse(struct wr_endpoint_device* dev);
int ep_sfp_enable(struct wr_endpoint_device* dev, int ena);
uint16_t ep_pcs_read(struct wr_endpoint_device* dev, int location);
void ep_pcs_write(struct wr_endpoint_device* dev, int location, int value);
void ep_reset_phy(struct wr_endpoint_device* dev);
void ep_pfilter_init_default(struct wr_endpoint_device* dev);
#endif
include/hw/endpoint_regs.h
View file @ e98a0cf1
......@@ -3,7 +3,7 @@
* File : endpoint_regs.h
* Author : auto-generated by wbgen2 from ep_wishbone_controller.wb
* Created : Fri Mar 15 17:03:12 2013
* Created : Thu Aug 20 14:59:12 2020
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
......@@ -14,7 +14,11 @@
#ifndef __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#define __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -48,6 +52,9 @@
/* definitions for field: Receive path enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Generate preamble shrinkage in reg: Endpoint Control Register */
#define EP_ECR_TXSHRIN_EN WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Feature present: VLAN tagging in reg: Endpoint Control Register */
#define EP_ECR_FEAT_VLAN WBGEN2_GEN_MASK(24, 1)
......@@ -60,6 +67,9 @@
/* definitions for field: Feature present: DPI packet classifier in reg: Endpoint Control Register */
#define EP_ECR_FEAT_DPI WBGEN2_GEN_MASK(27, 1)
/* definitions for field: Feature present: low phase drift calibration in reg: Endpoint Control Register */
#define EP_ECR_FEAT_LPC WBGEN2_GEN_MASK(28, 1)
/* definitions for register: Timestamping Control Register */
/* definitions for field: Transmit timestamping enable in reg: Timestamping Control Register */
......@@ -131,17 +141,17 @@
/* definitions for register: VLAN Control Register 1 */
/* definitions for field: Egress untagged set bitmap VID in reg: VLAN Control Register 1 */
#define EP_VCR1_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define EP_VCR1_VID_SHIFT 0
#define EP_VCR1_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define EP_VCR1_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: VLAN Untagged Set/Injection Buffer offset in reg: VLAN Control Register 1 */
#define EP_VCR1_OFFSET_MASK WBGEN2_GEN_MASK(0, 10)
#define EP_VCR1_OFFSET_SHIFT 0
#define EP_VCR1_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 10)
#define EP_VCR1_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 10)
/* definitions for field: Egress untagged set bitmap value in reg: VLAN Control Register 1 */
#define EP_VCR1_VALUE_MASK WBGEN2_GEN_MASK(12, 1)
#define EP_VCR1_VALUE_SHIFT 12
#define EP_VCR1_VALUE_W(value) WBGEN2_GEN_WRITE(value, 12, 1)
#define EP_VCR1_VALUE_R(reg) WBGEN2_GEN_READ(reg, 12, 1)
/* definitions for field: VLAN Untagged Set/Injection Buffer value in reg: VLAN Control Register 1 */
#define EP_VCR1_DATA_MASK WBGEN2_GEN_MASK(10, 18)
#define EP_VCR1_DATA_SHIFT 10
#define EP_VCR1_DATA_W(value) WBGEN2_GEN_WRITE(value, 10, 18)
#define EP_VCR1_DATA_R(reg) WBGEN2_GEN_READ(reg, 10, 18)
/* definitions for register: Packet Filter Control Register 0 */
......@@ -184,12 +194,18 @@
/* definitions for register: Flow Control Register */
/* definitions for field: RX Pause enable in reg: Flow Control Register */
/* definitions for field: RX Pause 802.3 enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX Pause enable in reg: Flow Control Register */
/* definitions for field: TX Pause 802.3 enable in reg: Flow Control Register */
#define EP_FCR_TXPAUSE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Rx Pause 802.1Q enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE_802_1Q WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Tx Pause 802.1Q enable (not implemented) in reg: Flow Control Register */
#define EP_FCR_TXPAUSE_802_1Q WBGEN2_GEN_MASK(3, 1)
/* definitions for field: TX pause threshold in reg: Flow Control Register */
#define EP_FCR_TX_THR_MASK WBGEN2_GEN_MASK(8, 8)
#define EP_FCR_TX_THR_SHIFT 8
......@@ -271,50 +287,69 @@
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BASE 0x00000080 /* base address */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
PACKED struct EP_WB {
/* [0x0]: REG Endpoint Control Register */
uint32_t ECR;
/* [0x4]: REG Timestamping Control Register */
uint32_t TSCR;
/* [0x8]: REG RX Deframer Control Register */
uint32_t RFCR;
/* [0xc]: REG VLAN control register 0 */
uint32_t VCR0;
/* [0x10]: REG VLAN Control Register 1 */
uint32_t VCR1;
/* [0x14]: REG Packet Filter Control Register 0 */
uint32_t PFCR0;
/* [0x18]: REG Packet Filter Control Register 1 */
uint32_t PFCR1;
/* [0x1c]: REG Traffic Class Assignment Register */
uint32_t TCAR;
/* [0x20]: REG Flow Control Register */
uint32_t FCR;
/* [0x24]: REG Endpoint MAC address high part register */
uint32_t MACH;
/* [0x28]: REG Endpoint MAC address low part register */
uint32_t MACL;
/* [0x2c]: REG MDIO Control Register */
uint32_t MDIO_CR;
/* [0x30]: REG MDIO Address/Status Register */
uint32_t MDIO_ASR;
/* [0x34]: REG Identification register */
uint32_t IDCODE;
/* [0x38]: REG Debug/Status register */
uint32_t DSR;
/* [0x3c]: REG DMTD Control Register */
uint32_t DMCR;
/* [0x40]: REG DMTD Status register */
uint32_t DMSR;
/* padding to: 32 words */
uint32_t __padding_0[15];
/* [0x80 - 0xff]: RAM Event counters memory, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t RMON_RAM [32];
};
/* definitions for register: PCK Injection CTRL */
/* definitions for field: Config: Interframe GAP in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_CONF_IFG_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_INJ_CTRL_PIC_CONF_IFG_SHIFT 0
#define EP_INJ_CTRL_PIC_CONF_IFG_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_INJ_CTRL_PIC_CONF_IFG_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Config: packet pattern sel id in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_CONF_SEL_MASK WBGEN2_GEN_MASK(16, 3)
#define EP_INJ_CTRL_PIC_CONF_SEL_SHIFT 16
#define EP_INJ_CTRL_PIC_CONF_SEL_W(value) WBGEN2_GEN_WRITE(value, 16, 3)
#define EP_INJ_CTRL_PIC_CONF_SEL_R(reg) WBGEN2_GEN_READ(reg, 16, 3)
/* definitions for field: Config: valid in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_CONF_VALID WBGEN2_GEN_MASK(19, 1)
/* definitions for field: Mode: packet generate mode in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_MODE_ID_MASK WBGEN2_GEN_MASK(20, 3)
#define EP_INJ_CTRL_PIC_MODE_ID_SHIFT 20
#define EP_INJ_CTRL_PIC_MODE_ID_W(value) WBGEN2_GEN_WRITE(value, 20, 3)
#define EP_INJ_CTRL_PIC_MODE_ID_R(reg) WBGEN2_GEN_READ(reg, 20, 3)
/* definitions for field: Mode: valid in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_MODE_VALID WBGEN2_GEN_MASK(23, 1)
/* definitions for field: Frame Generation Enabled in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_ENA WBGEN2_GEN_MASK(24, 1)
/* [0x0]: REG Endpoint Control Register */
#define EP_REG_ECR 0x00000000
/* [0x4]: REG Timestamping Control Register */
#define EP_REG_TSCR 0x00000004
/* [0x8]: REG RX Deframer Control Register */
#define EP_REG_RFCR 0x00000008
/* [0xc]: REG VLAN control register 0 */
#define EP_REG_VCR0 0x0000000c
/* [0x10]: REG VLAN Control Register 1 */
#define EP_REG_VCR1 0x00000010
/* [0x14]: REG Packet Filter Control Register 0 */
#define EP_REG_PFCR0 0x00000014
/* [0x18]: REG Packet Filter Control Register 1 */
#define EP_REG_PFCR1 0x00000018
/* [0x1c]: REG Traffic Class Assignment Register */
#define EP_REG_TCAR 0x0000001c
/* [0x20]: REG Flow Control Register */
#define EP_REG_FCR 0x00000020
/* [0x24]: REG Endpoint MAC address high part register */
#define EP_REG_MACH 0x00000024
/* [0x28]: REG Endpoint MAC address low part register */
#define EP_REG_MACL 0x00000028
/* [0x2c]: REG MDIO Control Register */
#define EP_REG_MDIO_CR 0x0000002c
/* [0x30]: REG MDIO Address/Status Register */
#define EP_REG_MDIO_ASR 0x00000030
/* [0x34]: REG Identification register */
#define EP_REG_IDCODE 0x00000034
/* [0x38]: REG Debug/Status register */
#define EP_REG_DSR 0x00000038
/* [0x3c]: REG DMTD Control Register */
#define EP_REG_DMCR 0x0000003c
/* [0x40]: REG DMTD Status register */
#define EP_REG_DMSR 0x00000040
/* [0x44]: REG PCK Injection CTRL */
#define EP_REG_INJ_CTRL 0x00000044
#endif
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