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Software for White Rabbit PTP Core
Commit d5c47372 authored by Peter Jansweijer's avatar Peter Jansweijer
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add ltc6950_ext_10mhz_config selection option

parent c54929c2
Pipeline #337 failed with stages
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      boards/spec7/board.c
      View file @ d5c47372
      ......@@ -22,6 +22,7 @@ static struct gpio_pin pin_pll_clk_sel = { &board.gpio_aux, 10 };
      static struct gpio_pin pin_eeprom_scl = { &board.gpio_aux, 11 };
      static struct gpio_pin pin_eeprom_sda = { &board.gpio_aux, 12 };
      #include "configs/ltc6950_defs.h"
      static struct ltc6950_config ltc6950_base_config =
      #include "configs/ltc6950_base_config.h"
      static struct ltc6950_config ltc6950_ext_10mhz_config =
      ......@@ -71,10 +72,19 @@ int spec7_init()
      {
      board_dbg("detect LTC6950: ID %x should be %x\n", id, 0x65 );
      } else {
      // Configuration for the SPEC7: Forward 125 MHz VCXO_REFCLK at CLK input to outputs 0, 1, 2
      ltc6950_configure(&board.ltc6950_pll, &ltc6950_base_config);
      // Set clock multiplexers (U63, U64) depending on WR mode
      spec7_set_pll_wr_mode(pll_wr_mode);
      if (pll_wr_mode == PLL_WR_MODE_MASTER | pll_wr_mode == PLL_WR_MODE_GM ) {
      // External 10 MHZ In (Bulls-Eye B03/B04) => 125 MHz (PLL_WR_MODE_GM) OR
      // 10 MHZ from TCXO (PLL_WR_MODE_MASTER) on outputs 0, 1, 2
      ltc6950_configure(&board.ltc6950_pll, &ltc6950_ext_10mhz_config);
      while ((ltc6950_read(&board.ltc6950_pll, 0x00) & LTC6950_LOCK) == 0);
      board_dbg("ltc6950 locked.\n");
      } else {
      // Forward 125 MHz VCXO_REFCLK at CLK input to outputs 0, 1, 2
      ltc6950_configure(&board.ltc6950_pll, &ltc6950_base_config);
      }
      }
      //while ((ltc6950_read( &board.ltc6950_pll, 0x16 ) &4) == 0);
      ......
      boards/spec7/configs/ltc6950_defs.h 0 → 100644
      View file @ d5c47372
      /* Define ltc6950 bit names */
      #define LTC6950_LOCK 4
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