Commit d4d8d2c8 authored by li hongming's avatar li hongming

Modify OUT9 to 125MHz (CLK output).

parent 30358b43
......@@ -257,7 +257,7 @@ int ad9516_init(int scb_version)
ad9516_set_output_divider(oc_spi_base, 3, 4, 0); // OUT3. 187.5 MHz. - not anymore
ad9516_set_output_divider(oc_spi_base, 4, 1, 0); // OUT4. 500 MHz.
ad9516_set_output_divider(oc_spi_base, 9, 20,0);
ad9516_set_output_divider(oc_spi_base, 9, 4,0); // OUT9. 125 MHz.
/*The following PLL outputs have been configured through the ad9516_base_config_34 register,
* so it doesn't need to replicate the configuration:
......
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