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Software for White Rabbit PTP Core
Commit c0ffd31c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'greg-wrs-low-jitter' into proposed_master

parents 780ed522 de1a914a
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Showing with 291 additions and 101 deletions
dev/ad9516.c
View file @ c0ffd31c
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dev/ad9516_config.h
View file @ c0ffd31c
...@@ -143,10 +143,85 @@ const struct ad9516_reg ad9516_base_config_34[] = { ...@@ -143,10 +143,85 @@ const struct ad9516_reg ad9516_base_config_34[] = {
{0x0231, 0x00}, {0x0231, 0x00},
}; };
/* Configuration for the SCB version greater than or equal 3.4: Base + 6, 7, 8, 9 outputs*/
const struct ad9516_reg ad9516_ljd_base_config[] = {
{0x0000, 0x99},
{0x0001, 0x00},
{0x0002, 0x10},
{0x0003, 0xC3},
{0x0004, 0x00},
{0x0010, 0x4C},
{0x0011, 0x00},
{0x0012, 0x00},
{0x0013, 0x06},
{0x0014, 0x12},
{0x0015, 0x00},
{0x0016, 0x04},
{0x0017, 0x00},
{0x0018, 0x07},
{0x0019, 0x00},
{0x001A, 0x00},
{0x001B, 0x00},
{0x001C, 0x01},
{0x001D, 0x00},
{0x001E, 0x00},
{0x001F, 0x0E},
{0x00A0, 0x01},
{0x00A1, 0x00},
{0x00A2, 0x00},
{0x00A3, 0x01},
{0x00A4, 0x00},
{0x00A5, 0x00},
{0x00A6, 0x01},
{0x00A7, 0x00},
{0x00A8, 0x00},
{0x00A9, 0x01},
{0x00AA, 0x00},
{0x00AB, 0x00},
{0x00F0, 0x0A},
{0x00F1, 0x0A},
{0x00F2, 0x0A},
{0x00F3, 0x0A},
{0x00F4, 0x08},
{0x00F5, 0x08},
// The following registers configure the PLL outputs from 6 to 9.
{0x0140, 0x42},
{0x0141, 0x42},
{0x0142, 0x08},
{0x0143, 0x4E},
{0x0190, 0x55},
{0x0191, 0x00},
{0x0192, 0x00},
{0x0193, 0x11},
{0x0194, 0x00},
{0x0195, 0x00},
{0x0196, 0x10},
{0x0197, 0x00},
{0x0198, 0x00},
{0x0199, 0x33},
{0x019A, 0x00},
{0x019B, 0x11},
{0x019C, 0x20},
{0x019D, 0x00},
{0x019E, 0x33},
{0x019F, 0x00},
{0x01A0, 0x11},
{0x01A1, 0x20},
{0x01A2, 0x00},
{0x01A3, 0x00},
//
{0x01E0, 0x01},
{0x01E1, 0x02},
{0x0230, 0x00},
{0x0231, 0x00},
};
/* Config for 25 MHz VCTCXO reference (RDiv = 5, use REF1) */ /* Config for 25 MHz VCTCXO reference (RDiv = 5, use REF1) */
const struct ad9516_reg ad9516_ref_tcxo[] = { const struct ad9516_reg ad9516_ref_tcxo[] = {
{0x0011, 0x05}, {0x0011, 0x05},
{0x0012, 0x00}, /* RDiv = 5 */ {0x0012, 0x00}, /* RDiv = 4 */
{0x001C, 0x06} /* Use REF1 */ {0x001C, 0x06} /* Use REF1 */
}; };
...@@ -157,3 +232,9 @@ const struct ad9516_reg ad9516_ref_ext[] = { ...@@ -157,3 +232,9 @@ const struct ad9516_reg ad9516_ref_ext[] = {
{0x001C, 0x46} /* Use REF1 */ {0x001C, 0x46} /* Use REF1 */
}; };
/* Config for Low-Jitter Daughterboard */
const struct ad9516_reg ad9516_ref_ljd[] = {
{0x0011, 0x04},
{0x0012, 0x00}, /* RDiv = 4 */
{0x001C, 0x06} /* Use REF1 */
};
include/board-wrs.h
View file @ c0ffd31c
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#define BASE_GPIO 0x10300 #define BASE_GPIO 0x10300
#define BASE_TIMER 0x10400 #define BASE_TIMER 0x10400
#define BASE_PPS_GEN 0x10500 #define BASE_PPS_GEN 0x10500
#define BASE_SPI_LJD_BOARD 0x10700
/* spll parameter that are board-specific */ /* spll parameter that are board-specific */
#define BOARD_DIVIDE_DMTD_CLOCKS 0 #define BOARD_DIVIDE_DMTD_CLOCKS 0
......
include/gpio-wrs.h
View file @ c0ffd31c
...@@ -10,6 +10,13 @@ ...@@ -10,6 +10,13 @@
#include "board.h" #include "board.h"
#define GPIO_SYS_CLK_SEL 0
#define GPIO_PLL_RESET_N 1
#define GPIO_PERIPH_RESET_N 3
#define GPIO_LJD_BOARD_DETECT 4
extern int ljd_present;
struct GPIO_WB struct GPIO_WB
{ {
uint32_t CODR; /*Clear output register*/ uint32_t CODR; /*Clear output register*/
...@@ -36,7 +43,7 @@ static inline void gpio_dir(int pin, int val) ...@@ -36,7 +43,7 @@ static inline void gpio_dir(int pin, int val)
__gpio->DDR &= ~(1<<pin); __gpio->DDR &= ~(1<<pin);
} }
static inline int gpio_in(int bank, int pin) static inline int gpio_in(int pin)
{ {
return __gpio->PSR & (1<<pin) ? 1: 0; return __gpio->PSR & (1<<pin) ? 1: 0;
} }
......
include/wrc.h
View file @ c0ffd31c
...@@ -70,7 +70,8 @@ extern int abs(int val); ...@@ -70,7 +70,8 @@ extern int abs(int val);
extern int wrc_ui_refperiod; extern int wrc_ui_refperiod;
/* Init functions and defaults for the wrs build */ /* Init functions and defaults for the wrs build */
int ad9516_init(int scb_ver); int ad9516_init(int scb_ver, int ljd_present);
int ljd_ad9516_init(void);
void rts_init(void); void rts_init(void);
int rtipc_init(void); int rtipc_init(void);
void rts_update(void); void rts_update(void);
......
softpll/softpll_ng.c
View file @ c0ffd31c
...@@ -32,7 +32,7 @@ volatile struct SPLL_WB *SPLL; ...@@ -32,7 +32,7 @@ volatile struct SPLL_WB *SPLL;
volatile struct PPSG_WB *PPSG; volatile struct PPSG_WB *PPSG;
int spll_n_chan_ref, spll_n_chan_out; int spll_n_chan_ref, spll_n_chan_out;
int ljd_present = 0; /* Low-jitter Daughterboard presence indicator */
#define MAIN_CHANNEL (spll_n_chan_ref) #define MAIN_CHANNEL (spll_n_chan_ref)
...@@ -485,12 +485,12 @@ void spll_show_stats() ...@@ -485,12 +485,12 @@ void spll_show_stats()
if (softpll.mode > 0) if (softpll.mode > 0)
pp_printf("softpll: irqs %d seq %s mode %d " pp_printf("softpll: irqs %d seq %s mode %d "
"alignment_state %d HL%d ML%d HY=%d MY=%d DelCnt=%d\n", "alignment_state %d HL%d ML%d HY=%d MY=%d DelCnt=%d setpoint:%d\n",
s->irq_count, statename, s->irq_count, statename,
s->mode, s->ext.align_state, s->mode, s->ext.align_state,
s->helper.ld.locked, s->mpll.ld.locked, s->helper.ld.locked, s->mpll.ld.locked,
s->helper.pi.y, s->mpll.pi.y, s->helper.pi.y, s->mpll.pi.y,
s->delock_count); s->delock_count, s->mpll.phase_shift_current);
} }
int spll_shifter_busy(int channel) int spll_shifter_busy(int channel)
...@@ -649,7 +649,7 @@ int spll_update() ...@@ -649,7 +649,7 @@ int spll_update()
return ret != 0; return ret != 0;
} }
static int spll_measure_frequency(int osc) int spll_measure_frequency(int osc)
{ {
volatile uint32_t *reg; volatile uint32_t *reg;
...@@ -667,7 +667,7 @@ static int spll_measure_frequency(int osc) ...@@ -667,7 +667,7 @@ static int spll_measure_frequency(int osc)
return 0; return 0;
} }
timer_delay_ms(2000); // timer_delay_ms(2000);
return (*reg ) & (0xfffffff); return (*reg ) & (0xfffffff);
} }
...@@ -699,20 +699,20 @@ static int calc_apr(int meas_min, int meas_max, int f_center ) ...@@ -699,20 +699,20 @@ static int calc_apr(int meas_min, int meas_max, int f_center )
void check_vco_frequencies() void check_vco_frequencies()
{ {
disable_irq(); //disable_irq();
int f_min, f_max; int f_min, f_max;
pll_verbose("SoftPLL VCO Frequency/APR test:\n"); pll_verbose("SoftPLL VCO Frequency/APR test:\n");
spll_set_dac(-1, 0); // spll_set_dac(-1, 0);
f_min = spll_measure_frequency(SPLL_OSC_DMTD); f_min = spll_measure_frequency(SPLL_OSC_DMTD);
spll_set_dac(-1, 65535); // spll_set_dac(-1, 65535);
f_max = spll_measure_frequency(SPLL_OSC_DMTD); f_max = spll_measure_frequency(SPLL_OSC_DMTD);
pll_verbose("DMTD VCO: Low=%d Hz Hi=%d Hz, APR = %d ppm.\n", f_min, f_max, calc_apr(f_min, f_max, 62500000)); pll_verbose("DMTD VCO: Low=%d Hz Hi=%d Hz, APR = %d ppm.\n", f_min, f_max, calc_apr(f_min, f_max, 62500000));
spll_set_dac(0, 0); // spll_set_dac(0, 0);
f_min = spll_measure_frequency(SPLL_OSC_REF); f_min = spll_measure_frequency(SPLL_OSC_REF);
spll_set_dac(0, 65535); // spll_set_dac(0, 65535);
f_max = spll_measure_frequency(SPLL_OSC_REF); f_max = spll_measure_frequency(SPLL_OSC_REF);
pll_verbose("REF VCO: Low=%d Hz Hi=%d Hz, APR = %d ppm.\n", f_min, f_max, calc_apr(f_min, f_max, REF_CLOCK_FREQ_HZ)); pll_verbose("REF VCO: Low=%d Hz Hi=%d Hz, APR = %d ppm.\n", f_min, f_max, calc_apr(f_min, f_max, REF_CLOCK_FREQ_HZ));
......
softpll/softpll_ng.h
View file @ c0ffd31c
...@@ -107,6 +107,7 @@ void spll_set_dac(int out_channel, int value); ...@@ -107,6 +107,7 @@ void spll_set_dac(int out_channel, int value);
int spll_get_dac(int out_channel); int spll_get_dac(int out_channel);
void check_vco_frequencies(void); void check_vco_frequencies(void);
int spll_measure_frequency(int osc);
/* /*
* Aux and main state: * Aux and main state:
...@@ -148,6 +149,7 @@ struct spll_fifo_log { ...@@ -148,6 +149,7 @@ struct spll_fifo_log {
}; };
#define FIFO_LOG_LEN 16 #define FIFO_LOG_LEN 16
extern int ljd_present;
#endif // __SOFTPLL_NG_H #endif // __SOFTPLL_NG_H
softpll/spll_external.c
View file @ c0ffd31c
...@@ -14,13 +14,14 @@ ...@@ -14,13 +14,14 @@
#include "softpll_ng.h" #include "softpll_ng.h"
#include "irq.h" #include "irq.h"
#define ALIGN_SAMPLE_PERIOD 100000 #define ALIGN_SAMPLE_PERIOD 100000
#define ALIGN_TARGET 0 #define ALIGN_TARGET 0
#define EXT_PERIOD_NS 100 #define EXT_PERIOD_NS 100
#define EXT_FREQ_HZ 10000000 #define EXT_FREQ_HZ 10000000
#define EXT_PPS_LATENCY_PS 30000 // fixme: make configurable // fixme: make configurable
#define EXT_PPS_LATENCY_PS 30000 // for regular ext channel
#define EXT_PPS_LATENCY_LJD_PS 63000 // for low-jitter daughterboard
void external_init(volatile struct spll_external_state *s, int ext_ref, void external_init(volatile struct spll_external_state *s, int ext_ref,
...@@ -28,6 +29,8 @@ void external_init(volatile struct spll_external_state *s, int ext_ref, ...@@ -28,6 +29,8 @@ void external_init(volatile struct spll_external_state *s, int ext_ref,
{ {
int idx = spll_n_chan_ref + spll_n_chan_out; int idx = spll_n_chan_ref + spll_n_chan_out;
if (ljd_present)
idx++;
helper_init(s->helper, idx); helper_init(s->helper, idx);
mpll_init(s->main, idx, spll_n_chan_ref); mpll_init(s->main, idx, spll_n_chan_ref);
...@@ -38,7 +41,7 @@ void external_init(volatile struct spll_external_state *s, int ext_ref, ...@@ -38,7 +41,7 @@ void external_init(volatile struct spll_external_state *s, int ext_ref,
void external_start(struct spll_external_state *s) void external_start(struct spll_external_state *s)
{ {
helper_start(s->helper); helper_start(s->helper);
SPLL->ECCR = SPLL_ECCR_EXT_EN; SPLL->ECCR = SPLL_ECCR_EXT_EN;
...@@ -50,10 +53,10 @@ void external_start(struct spll_external_state *s) ...@@ -50,10 +53,10 @@ void external_start(struct spll_external_state *s)
int external_locked(volatile struct spll_external_state *s) int external_locked(volatile struct spll_external_state *s)
{ {
if (!s->helper->ld.locked || !s->main->ld.locked || if (!s->helper->ld.locked || !s->main->ld.locked ||
!(SPLL->ECCR & SPLL_ECCR_EXT_REF_LOCKED) || // ext PLL became unlocked !(SPLL->ECCR & SPLL_ECCR_EXT_REF_LOCKED) || // ext PLL became unlocked
(SPLL->ECCR & SPLL_ECCR_EXT_REF_STOPPED)) // 10MHz unplugged (only SPEC) (SPLL->ECCR & SPLL_ECCR_EXT_REF_STOPPED)) // 10MHz unplugged (only SPEC)
return 0; return 0;
switch(s->align_state) { switch(s->align_state) {
case ALIGN_STATE_EXT_OFF: case ALIGN_STATE_EXT_OFF:
case ALIGN_STATE_WAIT_CLKIN: case ALIGN_STATE_WAIT_CLKIN:
...@@ -83,27 +86,53 @@ static int align_sample(int channel, int *v) ...@@ -83,27 +86,53 @@ static int align_sample(int channel, int *v)
return 0; // sample not valid return 0; // sample not valid
} }
static inline int get_pps_latency(int sel)
{
if (sel)
return EXT_PPS_LATENCY_LJD_PS;
else
return EXT_PPS_LATENCY_PS;
}
int external_align_fsm(volatile struct spll_external_state *s) int external_align_fsm(volatile struct spll_external_state *s)
{ {
int v, done_sth = 0; int v, done_sth = 0;
static int timeout;
switch(s->align_state) { switch(s->align_state) {
case ALIGN_STATE_EXT_OFF: case ALIGN_STATE_EXT_OFF:
break; break;
case ALIGN_STATE_WAIT_CLKIN: case ALIGN_STATE_WAIT_CLKIN:
if( !(SPLL->ECCR & SPLL_ECCR_EXT_REF_STOPPED) ) { if(!ljd_present && !(SPLL->ECCR & SPLL_ECCR_EXT_REF_STOPPED) ) {
SPLL->ECCR |= SPLL_ECCR_EXT_REF_PLLRST; SPLL->ECCR |= SPLL_ECCR_EXT_REF_PLLRST;
s->align_state = ALIGN_STATE_WAIT_PLOCK; s->align_state = ALIGN_STATE_WAIT_PLOCK;
done_sth++; done_sth++;
} }
#if defined(CONFIG_WR_SWITCH)
else if (ljd_present) {
uint32_t f_ext;
int ljd_ad9516_stat;
/* reset ljd ad9516 */
SPLL->ECCR |= SPLL_ECCR_EXT_REF_PLLRST;
timer_delay(10);
SPLL->ECCR &= (~SPLL_ECCR_EXT_REF_PLLRST);
timer_delay(10);
ljd_ad9516_stat = ljd_ad9516_init();
f_ext = spll_measure_frequency(SPLL_OSC_EXT);
if (!ljd_ad9516_stat && (f_ext > 9999000) && (f_ext < 10001000)) {
s->align_state = ALIGN_STATE_WAIT_PLOCK;
pp_printf("External AD9516 locked\n");
}
}
#endif
break; break;
case ALIGN_STATE_WAIT_PLOCK: case ALIGN_STATE_WAIT_PLOCK:
SPLL->ECCR &= (~SPLL_ECCR_EXT_REF_PLLRST); SPLL->ECCR &= (~SPLL_ECCR_EXT_REF_PLLRST);
if( SPLL->ECCR & SPLL_ECCR_EXT_REF_STOPPED ) if(SPLL->ECCR & SPLL_ECCR_EXT_REF_STOPPED )
s->align_state = ALIGN_STATE_WAIT_CLKIN; s->align_state = ALIGN_STATE_WAIT_CLKIN;
else if( SPLL->ECCR & SPLL_ECCR_EXT_REF_LOCKED ) else if(SPLL->ECCR & SPLL_ECCR_EXT_REF_LOCKED)
s->align_state = ALIGN_STATE_START; s->align_state = ALIGN_STATE_START;
done_sth++; done_sth++;
break; break;
...@@ -115,6 +144,9 @@ int external_align_fsm(volatile struct spll_external_state *s) ...@@ -115,6 +144,9 @@ int external_align_fsm(volatile struct spll_external_state *s)
enable_irq(); enable_irq();
s->align_state = ALIGN_STATE_START_MAIN; s->align_state = ALIGN_STATE_START_MAIN;
done_sth++; done_sth++;
} else if (time_after(timer_get_tics(), timeout + 5*TICS_PER_SECOND)) {
pll_verbose("EXT: timeout, restarting\n");
s->align_state = ALIGN_STATE_WAIT_CLKIN;
} }
break; break;
...@@ -127,6 +159,9 @@ int external_align_fsm(volatile struct spll_external_state *s) ...@@ -127,6 +159,9 @@ int external_align_fsm(volatile struct spll_external_state *s)
s->align_state = ALIGN_STATE_INIT_CSYNC; s->align_state = ALIGN_STATE_INIT_CSYNC;
pll_verbose("EXT: DMTD locked.\n"); pll_verbose("EXT: DMTD locked.\n");
done_sth++; done_sth++;
} else if (time_after(timer_get_tics(), timeout + 5*TICS_PER_SECOND)) {
pll_verbose("EXT: timeout, restarting\n");
s->align_state = ALIGN_STATE_WAIT_CLKIN;
} }
break; break;
...@@ -171,8 +206,8 @@ int external_align_fsm(volatile struct spll_external_state *s) ...@@ -171,8 +206,8 @@ int external_align_fsm(volatile struct spll_external_state *s)
s->align_shift += s->align_step; s->align_shift += s->align_step;
mpll_set_phase_shift(s->main, s->align_shift); mpll_set_phase_shift(s->main, s->align_shift);
} else if (v == s->align_target) { } else if (v == s->align_target) {
s->align_shift += EXT_PPS_LATENCY_PS; s->align_shift += get_pps_latency(ljd_present);
mpll_set_phase_shift(s->main, s->align_shift); mpll_set_phase_shift(s->main, s->align_shift);
s->align_state = ALIGN_STATE_COMPENSATE_DELAY; s->align_state = ALIGN_STATE_COMPENSATE_DELAY;
} }
done_sth++; done_sth++;
...@@ -197,5 +232,8 @@ int external_align_fsm(volatile struct spll_external_state *s) ...@@ -197,5 +232,8 @@ int external_align_fsm(volatile struct spll_external_state *s)
default: default:
break; break;
} }
if (done_sth > 0) {
timeout = timer_get_tics();
}
return done_sth != 0; return done_sth != 0;
} }
softpll/spll_helper.c
View file @ c0ffd31c
...@@ -17,8 +17,13 @@ void helper_init(struct spll_helper_state *s, int ref_channel) ...@@ -17,8 +17,13 @@ void helper_init(struct spll_helper_state *s, int ref_channel)
/* Phase branch PI controller */ /* Phase branch PI controller */
s->pi.y_min = 5; s->pi.y_min = 5;
s->pi.y_max = (1 << DAC_BITS) - 5; s->pi.y_max = (1 << DAC_BITS) - 5;
#if defined(CONFIG_WR_NODE)
s->pi.kp = -150;//(int)(0.3 * 32.0 * 16.0); // / 2; s->pi.kp = -150;//(int)(0.3 * 32.0 * 16.0); // / 2;
s->pi.ki = -2;//(int)(0.03 * 32.0 * 3.0); // / 2; s->pi.ki = -2;//(int)(0.03 * 32.0 * 3.0); // / 2;
#else
s->pi.kp = 150;
s->pi.ki = 2;
#endif
s->pi.anti_windup = 1; s->pi.anti_windup = 1;
/* Phase branch lock detection */ /* Phase branch lock detection */
...@@ -83,8 +88,11 @@ void helper_start(struct spll_helper_state *s) ...@@ -83,8 +88,11 @@ void helper_start(struct spll_helper_state *s)
{ {
/* Set the bias to the upper end of tuning range. This is to ensure that /* Set the bias to the upper end of tuning range. This is to ensure that
the HPLL will always lock on positive frequency offset. */ the HPLL will always lock on positive frequency offset. */
#if defined(CONFIG_WR_SWITCH)
s->pi.bias = s->pi.y_max;
#else
s->pi.bias = s->pi.y_min; s->pi.bias = s->pi.y_min;
#endif
s->p_setpoint = 0; s->p_setpoint = 0;
s->p_adder = 0; s->p_adder = 0;
s->sample_n = 0; s->sample_n = 0;
......
softpll/spll_main.c
View file @ c0ffd31c
...@@ -31,8 +31,13 @@ void mpll_init(struct spll_main_state *s, int id_ref, ...@@ -31,8 +31,13 @@ void mpll_init(struct spll_main_state *s, int id_ref,
s->pi.anti_windup = 1; s->pi.anti_windup = 1;
s->pi.bias = 30000; s->pi.bias = 30000;
#if defined(CONFIG_WR_SWITCH) #if defined(CONFIG_WR_SWITCH)
s->pi.kp = -1100; // / 2; if (ljd_present) {
s->pi.ki = -30; // / 2; s->pi.kp = 2000;
s->pi.ki = 15;
} else {
s->pi.kp = 1100; // / 2;
s->pi.ki = 30; // / 2;
}
#elif defined(CONFIG_WR_NODE) #elif defined(CONFIG_WR_NODE)
s->pi.kp = -1100; // / 2; s->pi.kp = -1100; // / 2;
s->pi.ki = -30; // / 2; s->pi.ki = -30; // / 2;
...@@ -157,11 +162,19 @@ int mpll_update(struct spll_main_state *s, int tag, int source) ...@@ -157,11 +162,19 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
if (s->ld.locked) { if (s->ld.locked) {
if (s->phase_shift_current < s->phase_shift_target) { if (s->phase_shift_current < s->phase_shift_target) {
s->phase_shift_current++; s->phase_shift_current++;
#if defined(CONFIG_WR_SWITCH)
s->adder_ref++;
#else
s->adder_ref--; s->adder_ref--;
#endif
} else if (s->phase_shift_current > } else if (s->phase_shift_current >
s->phase_shift_target) { s->phase_shift_target) {
s->phase_shift_current--; s->phase_shift_current--;
#if defined(CONFIG_WR_SWITCH)
s->adder_ref--;
#else
s->adder_ref++; s->adder_ref++;
#endif
} }
} }
if (ld_update((spll_lock_det_t *)&s->ld, err)) if (ld_update((spll_lock_det_t *)&s->ld, err))
......
softpll/spll_ptracker.c
View file @ c0ffd31c
...@@ -56,8 +56,11 @@ int ptrackers_update(struct spll_ptracker_state *ptrackers, int tag, ...@@ -56,8 +56,11 @@ int ptrackers_update(struct spll_ptracker_state *ptrackers, int tag,
if(!s->enabled) if(!s->enabled)
return 0; return 0;
#if defined(CONFIG_WR_NODE)
register int delta = (tag - tag_ref) & ((1 << HPLL_N) - 1); register int delta = (tag - tag_ref) & ((1 << HPLL_N) - 1);
#else
register int delta = (tag_ref - tag) & ((1 << HPLL_N) - 1);
#endif
register int index = delta >> (HPLL_N - 2); register int index = delta >> (HPLL_N - 2);
......
wrs_main.c
View file @ c0ffd31c
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include "minipc.h" #include "minipc.h"
#include "revision.h" #include "revision.h"
#include "system_checks.h" #include "system_checks.h"
#include "gpio-wrs.h"
int scb_ver = 33; /* SCB version */ int scb_ver = 33; /* SCB version */
...@@ -40,6 +41,12 @@ int main(void) ...@@ -40,6 +41,12 @@ int main(void)
build_revision, build_date, build_time); build_revision, build_date, build_time);
pp_printf("SCB version: %d. %s\n", scb_ver,(scb_ver>=34)?"10 MHz SMC Output.":"" ); pp_printf("SCB version: %d. %s\n", scb_ver,(scb_ver>=34)?"10 MHz SMC Output.":"" );
pp_printf("Start counter %d\n", stats.start_cnt); pp_printf("Start counter %d\n", stats.start_cnt);
/* Low-jitter Daughterboard detection */
ljd_present = gpio_in(GPIO_LJD_BOARD_DETECT);
if (ljd_present) {
pp_printf("\n--- WRS Low jitter board detected. ---\n");
pp_printf("Allow 1 hour of warming up before starting measurements\n");
}
pp_printf("--\n"); pp_printf("--\n");
if (stats.start_cnt > 1) { if (stats.start_cnt > 1) {
...@@ -47,7 +54,7 @@ int main(void) ...@@ -47,7 +54,7 @@ int main(void)
/* for sure problem is in calling second time ad9516_init, /* for sure problem is in calling second time ad9516_init,
* but not only */ * but not only */
} }
ad9516_init(scb_ver); ad9516_init(scb_ver, ljd_present);
rts_init(); rts_init();
rtipc_init(); rtipc_init();
spll_very_init(); spll_very_init();
......
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