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Software for White Rabbit PTP Core
Commit c047feb5 authored by Tristan Gingold's avatar Tristan Gingold
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softpll: adjust values for hw dithering 

Now enabled on wr2rf
parent a6163f47
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Showing with 23 additions and 16 deletions
boards/ertm14/board.h
View file @ c047feb5
......@@ -71,6 +71,7 @@
#define BOARD_MAX_CHAN_AUX 2
#define BOARD_MAX_PTRACKERS 1
#define BOARD_SPLL_DIV_BITS 8
#define BOARD_SPLL_DAC_BITS 24
#define ERTM14_MAX_CONFIGS 8
......
boards/wr2rf-vme/board-config.h
View file @ c047feb5
......@@ -43,6 +43,12 @@
#define BOARD_MAX_CHAN_AUX 1 /* No extra vcxo */
#define BOARD_MAX_PTRACKERS 1
/* Hardware dithering: wrc_dac_dither convert from 24b to 16b.
DIV_BITS is the number of bits eaten by hardware dithering,
DAC_BITS is the number of virtual dac bits (before hw dithering). */
#define BOARD_SPLL_DIV_BITS 8
#define BOARD_SPLL_DAC_BITS (16 + BOARD_SPLL_DIV_BITS)
#define CONFIG_SPLL_DEGLITCH_THR 550
#define SDBFS_REC 5
......
boards/wr2rf-vme/board.c
View file @ c047feb5
......@@ -64,17 +64,17 @@ static void wr2rf_spll_setup(void)
gs->stages[0].kp = -4000 * 16;
gs->stages[0].ki = -5 * 16;
gs->stages[0].lock_samples = 30000;
gs->stages[0].shift = 8;
gs->stages[0].shift = 16 - BOARD_SPLL_DIV_BITS;
/* once it's locked, the loop bandwidth is switched to ~0.1 Hz to filter out WR link added phase noise */
gs->stages[1].kp = -3000;
gs->stages[1].ki = -5;
gs->stages[1].lock_samples = 10000;
gs->stages[1].shift = 8;
gs->stages[1].shift = 16 - BOARD_SPLL_DIV_BITS;
spll_set_gain_schedule( gs );
spll_set_pi_gain( SPLL_LOOP_HELPER, 0, -700, -2, 8 );
spll_set_gain_schedule( gs );
spll_set_pi_gain( SPLL_LOOP_HELPER, 0,
-150, -2, PI_FRACBITS - BOARD_SPLL_DIV_BITS );
// Aux clock 0 is used for 'factory' calibration of CLKAB/LO/REF outputs.
spll_set_aux_mode( 0, SPLL_AUX_MODE_PHASE_MONITOR );
......
include/spll_defs.h
View file @ c047feb5
......@@ -50,8 +50,8 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia
/* Maximum MPLL loop gain scheduler levels */
#define SPLL_GAIN_SCHED_MAX 2
#if defined( BOARD_SPLL_DAC_BITS )
#define DAC_BITS BOARD_SPLL_DAC_BITS
#else
#define DAC_BITS 16
/* Default number of DAC bits, no hardware dithering. */
#ifndef BOARD_SPLL_DAC_BITS
# define BOARD_SPLL_DAC_BITS 16
# define BOARD_SPLL_DIV_BITS 0
#endif
softpll/spll_helper.c
View file @ c047feb5
......@@ -14,8 +14,8 @@
void helper_very_init( struct spll_helper_state *s )
{
/* Phase branch PI controller */
s->pi.y_min = 5;
s->pi.y_max = (1 << DAC_BITS) - 5;
s->pi.y_min = (5 << BOARD_SPLL_DIV_BITS);
s->pi.y_max = (1 << BOARD_SPLL_DAC_BITS) - (5 << BOARD_SPLL_DIV_BITS);
#if defined(CONFIG_WR_NODE)
s->pi.kp = -150;
s->pi.ki = -2;
......@@ -23,7 +23,7 @@ void helper_very_init( struct spll_helper_state *s )
s->pi.kp = 150;
s->pi.ki = 2;
#endif
s->pi.shift = PI_FRACBITS;
s->pi.shift = PI_FRACBITS - BOARD_SPLL_DIV_BITS;
s->pi.anti_windup = 1;
/* Phase branch lock detection */
......
softpll/spll_main.c
View file @ c047feb5
......@@ -28,11 +28,11 @@ void mpll_init(struct spll_main_state *s, int id_ref, int id_out)
s->ps_freeze = 0;
s->vco_freeze = 0;
s->pi.y_min = 5;
s->pi.y_max = (1 << DAC_BITS) - 5;
s->pi.y_min = (5 << BOARD_SPLL_DIV_BITS);
s->pi.y_max = (1 << BOARD_SPLL_DAC_BITS) - (5 << BOARD_SPLL_DIV_BITS);
s->pi.anti_windup = 1;
s->pi.bias = (1 << (DAC_BITS - 1) ); // midscale
s->pi.shift = PI_FRACBITS;
s->pi.bias = (1 << (BOARD_SPLL_DAC_BITS - 1)); // midscale
s->pi.shift = PI_FRACBITS - BOARD_SPLL_DIV_BITS;
#if defined(CONFIG_TARGET_WR_SWITCH)
if (spll_ljd_present) {
s->pi.kp = 2000;
......
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