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Software for White Rabbit PTP Core
Commit a88ce3d3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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boards: port SIS83k support to wrpc-sw-v5

parent 82afd020
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Kconfig
View file @ a88ce3d3
......@@ -29,6 +29,11 @@ config TARGET_ERTM14
help
eRTM14/15 MTCA.4 WR Receiver (Kintex-7)
config TARGET_SIS8300KU
bool "Struck SIS8300KU MTCA.4 Card"
help
Struck SIS8300KU MTCA.4 Card (Kintex Ultrascale)
endchoice
config WR_NODE
......
boards/boards.mk
View file @ a88ce3d3
......@@ -2,5 +2,13 @@ obj-$(CONFIG_TARGET_GENERIC_PHY_8BIT) += boards/generic/board.o
obj-$(CONFIG_TARGET_GENERIC_PHY_16BIT) += boards/generic/board.o
obj-$(CONFIG_TARGET_WR_SWITCH) += boards/wr-switch/main.o boards/wr-switch/gpio-wrs.o boards/wr-switch/ad9516.o
obj-$(CONFIG_TARGET_AFCZ) += boards/afcz/board.o
obj-$(CONFIG_TARGET_SIS8300KU) += boards/sis8300ku/board.o
obj-$(CONFIG_TARGET_ERTM14) += boards/ertm14/board.o boards/ertm14/ertm15_rf_distr.o boards/ertm14/phy_calibration.o boards/ertm14/rf_frame_transceiver.o boards/ertm14/cmd_ertm14.o
#boards/sis8300ku/board.o: boards/sis8300ku/sdbfs-image.h
#./tools/gensdbfs -c boards/sis8300ku/sdbfs-image.h boards/sis8300ku/sdbfs boards/sis8300ku/sdbfs-image.bin
#obj-$(CONFIG_TARGET_SIS8300KU): boards/sis8300ku/sdbfs-image.h
# echo "DUPA"
# sleep 10
# #
boards/sis8300ku/board.c 0 → 100644
View file @ a88ce3d3
#include "board.h"
#include "dev/bb_spi.h"
#include "dev/spi_flash.h"
#include "dev/syscon.h"
#include "softpll_ng.h"
#include "storage.h"
#include <wrc-event.h>
extern uint32_t sdbfs_default_bin[] =
{
#include "sdbfs-image.h"
};
static const int32_t flash_entry_points[] = { 0x0f00000, -1 };
int wrc_board_early_init()
{
int memtype;
uint32_t sdbfs_entry;
/*
* declare GPIO pins and configure their directions for bit-banging SPI
* limit SPI speed to 10MHz by setting bit_delay = CPU_CLOCK / 10^6
*/
bb_spi_create( &spi_wrc_flash,
&pin_sysc_spi_ncs,
&pin_sysc_spi_mosi,
&pin_sysc_spi_miso,
&pin_sysc_spi_sclk, CPU_CLOCK / 10000000 );
spi_wrc_flash.rd_falling_edge = 1;
/*
* Initialize SPI flash and read its ID
*/
spi_flash_create( &wrc_flash_dev, &spi_wrc_flash, 0x10000, 0xf00000);
wrc_flash_dev.use_4byte_addr = 0;
wrc_flash_dev.size = 0x1000000; // 32 MB flash
uint32_t id = spi_flash_read_id( &wrc_flash_dev );
if( id != 0x00012018 && id != 0xC22019 )
{
pp_printf("Can't find a matching flash memory. Read ID = 0x%08x\n", id);
return 0;
}
/*
* Initialize storage subsystem with newly created SPI Flash
*/
storage_spiflash_create( &wrc_storage_dev, &wrc_flash_dev );
// override default entry point for the flash
wrc_storage_dev.entry_points = flash_entry_points;
/*
* Mount SDBFS filesystem from storage.
*/
storage_mount( &wrc_storage_dev );
// fixme: read MAC address from the MMC
uint8_t mac[6];
get_persistent_mac(0, mac);
board_dbg("Board MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
ep_set_mac_addr( mac );
spll_set_aux_mode( 0, SPLL_AUX_MODE_TRACKING_SOURCE );
spll_set_aux_mode( 1, SPLL_AUX_MODE_TRACKING_SOURCE );
return 0;
}
static int sis83k_handle_event( int event )
{
if ( event == WRC_EVENT_LINK_DOWN )
{
// fixme: do we need forced PHY reset here?
}
}
int wrc_board_init()
{
event_handler_register( 1 << WRC_EVENT_LINK_DOWN, 1, sis83k_handle_event );
return 0;
}
int wrc_board_create_tasks()
{
return 0;
}
boards/sis8300ku/board.h 0 → 100644
View file @ a88ce3d3
/*
* This work is part of the White Rabbit project
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#ifndef __BOARD_WRC_H
#define __BOARD_WRC_H
/*
* This is meant to be automatically included by the Makefile,
* when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch)
*/
#define BOARD_USE_CUSTOM_SDBFS 1
/* Fixed base addresses */
#define BASE_MINIC 0x20000
#define BASE_EP 0x20100
#define BASE_SOFTPLL 0x20200
#define BASE_PPS_GEN 0x20300
#define BASE_SYSCON 0x20400
#define BASE_UART 0x20500
#define BASE_ONEWIRE 0x20600
//#define BASE_ETHERNOBE_CFG 0x20700
/* Board-specific parameters */
#define TICS_PER_SECOND 1000
/* WR Core system/CPU clock frequency in Hz */
#define CPU_CLOCK 62500000ULL
/* WR Reference clock period (picoseconds) and frequency (Hz) */
#define NS_PER_CLOCK 16
#define REF_CLOCK_PERIOD_PS 16000
#define REF_CLOCK_FREQ_HZ 62500000
/* Baud rate of the builtin UART (does not apply to the VUART) */
#define UART_BAUDRATE 115200ULL
/* Maximum number of simultaneously created sockets */
#define NET_MAX_SOCKETS 12
/* Socket buffer size, determines the max. RX packet size */
#define NET_MAX_SKBUF_SIZE 512
/* Number of auxillary clock channels - usually equal to the number of FMCs */
#define NUM_AUX_CLOCKS 1
/* spll parameter that are board-specific */
#define BOARD_DIVIDE_DMTD_CLOCKS 0
#define BOARD_MAX_CHAN_REF 1
#define BOARD_MAX_CHAN_AUX 2
#define BOARD_MAX_PTRACKERS 1
#ifdef CONFIG_IP
#define HAS_IP 1
#else
#define HAS_IP 0
#endif
#ifdef CONFIG_ABSCAL
#define HAS_ABSCAL 1
#else
#define HAS_ABSCAL 0
#endif
#define CONFIG_DISALLOW_LONG_DIVISION
#define BOARD_MAX_CONSOLE_DEVICES 1
#define CONSOLE_UART_BAUDRATE 115200
#define SDB_ADDRESS 0x30000
#define FMC_EEPROM_ADR 0x50
#define SDBFS_REC 6
void sdb_find_devices(void);
void sdb_print_devices(void);
#endif /* __BOARD_WRC_H */
boards/sis8300ku/sdbfs-image.h 0 → 100644
View file @ a88ce3d3
// generated by tools/gensdbfs. Don't hand-edit unless you know what you're doing...
0x5344422D,
0x00050101,
0x00000000,
0x00000000,
0x00000000,
0x00F40005,
0x46696C65,
0x44617461,
0x2E202020,
0x00000001,
0x00000000,
0x2E202020,
0x20202020,
0x20202020,
0x20202020,
0x20202000,
0x00000000,
0x00000006,
0x00000000,
0x00F20000,
0x00000000,
0x00F2FFFF,
0x46696C65,
0x44617461,
0x7366702D,
0x00000001,
0x00000000,
0x7366702D,
0x64617461,
0x62617365,
0x20202020,
0x20202001,
0x00000000,
0x00000006,
0x00000000,
0x00F10000,
0x00000000,
0x00F1FFFF,
0x46696C65,
0x44617461,
0x77722D69,
0x00000001,
0x00000000,
0x77722D69,
0x6E697420,
0x20202020,
0x20202020,
0x20202001,
0x00000000,
0x00000006,
0x00000000,
0x00F40000,
0x00000000,
0x00F40005,
0x46696C65,
0x44617461,
0x6D61632D,
0x00000001,
0x00000000,
0x6D61632D,
0x61646472,
0x65737320,
0x20202020,
0x20202001,
0x00000000,
0x00000006,
0x00000000,
0x00F30000,
0x00000000,
0x00F3FFFF,
0x46696C65,
0x44617461,
0x63616C69,
0x00000001,
0x00000000,
0x63616C69,
0x62726174,
0x696F6E20,
0x20202020,
0x20202001
boards/sis8300ku/sdbfs/--SDB-CONFIG-- 0 → 100644
View file @ a88ce3d3
#
# We want to store WRPC parameters but also the FPGA bitstream in the same
# FLASH. That is why our default position for various parameters is right after
# the bitstream.
position = 0x0
# Allocation granularity is 64 bytes
# We start with bitstream file at position 0, later the same set of files as for
# EEPROM image is used.
wr-init
write = 1
position = 0x0f10000
maxsize = 0x10000
# each sfp takes 29 bytes, 4 of them fit in 128 bytes
sfp-database
write = 1
position = 0x0f20000
maxsize = 0x10000
calibration
write = 1
position = 0x0f30000
maxsize = 0x10000
mac-address
write = 1
maxsize = 6
position = 0x0f40000
include/board.h
View file @ a88ce3d3
......@@ -25,9 +25,12 @@
# include "boards/afcz/board.h"
#elif defined(CONFIG_TARGET_ERTM14)
# include "boards/ertm14/board.h"
#elif defined(CONFIG_TARGET_SIS8300KU)
# include "boards/sis8300ku/board.h"
#endif
int wrc_board_early_init(void);
int wrc_board_init(void);
int wrc_board_create_tasks(void);
......
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