Commit a81832bc authored by Tristan Gingold's avatar Tristan Gingold

move target_sis8300ku_defconfig to risc-v

parent 471ba3c4
Pipeline #4489 failed with stage
in 2 minutes and 40 seconds
......@@ -64,7 +64,7 @@ int wrc_board_early_init()
wrc_flash_dev.use_4byte_addr = 0;
wrc_flash_dev.size = 0x1000000; // 32 MB flash
uint32_t id = spi_flash_read_id( &wrc_flash_dev );
unsigned id = spi_flash_read_id( &wrc_flash_dev );
if( id != 0x00012018 && id != 0xC22019 )
{
......
......@@ -2,8 +2,8 @@
# Automatically generated file; DO NOT EDIT.
# WR PTP Core software configuration
#
CONFIG_ARCH_LM32=y
# CONFIG_ARCH_RISCV is not set
# CONFIG_ARCH_LM32=y
CONFIG_ARCH_RISCV=y
# CONFIG_TARGET_GENERIC_PHY_8BIT is not set
# CONFIG_TARGET_GENERIC_PHY_16BIT is not set
# CONFIG_TARGET_WR_SWITCH is not set
......
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