Commit 9a5110dd authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

snmp: export board name from HDL register

parent 9db811ce
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
*/ */
#include "syscon.h" #include "syscon.h"
#include <errno.h> #include <errno.h>
#include <string.h>
struct s_i2c_if i2c_if[2] = { struct s_i2c_if i2c_if[2] = {
{SYSC_GPSR_FMC_SCL, SYSC_GPSR_FMC_SDA}, {SYSC_GPSR_FMC_SCL, SYSC_GPSR_FMC_SDA},
...@@ -16,6 +17,17 @@ struct s_i2c_if i2c_if[2] = { ...@@ -16,6 +17,17 @@ struct s_i2c_if i2c_if[2] = {
volatile struct SYSCON_WB *syscon; volatile struct SYSCON_WB *syscon;
/****************************
* BOARD NAME
***************************/
void get_hw_name(char *str)
{
uint32_t val;
val = syscon->HWIR;
memcpy(str, &val, HW_NAME_LENGTH-1);
}
/**************************** /****************************
* TIMER * TIMER
***************************/ ***************************/
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h * File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb * Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Mon Apr 24 17:41:58 2017 * Created : Mon Jul 3 13:40:08 2017
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
...@@ -127,6 +127,14 @@ ...@@ -127,6 +127,14 @@
#define SYSC_HWFR_MEMSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 4) #define SYSC_HWFR_MEMSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define SYSC_HWFR_MEMSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 4) #define SYSC_HWFR_MEMSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for register: Hardware Info Register */
/* definitions for field: Board name in reg: Hardware Info Register */
#define SYSC_HWIR_NAME_MASK WBGEN2_GEN_MASK(0, 32)
#define SYSC_HWIR_NAME_SHIFT 0
#define SYSC_HWIR_NAME_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SYSC_HWIR_NAME_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Timer Control Register */ /* definitions for register: Timer Control Register */
/* definitions for field: Timer Divider in reg: Timer Control Register */ /* definitions for field: Timer Divider in reg: Timer Control Register */
...@@ -259,54 +267,56 @@ ...@@ -259,54 +267,56 @@
#define SYSC_REG_GPCR 0x00000008 #define SYSC_REG_GPCR 0x00000008
/* [0xc]: REG Hardware Feature Register */ /* [0xc]: REG Hardware Feature Register */
#define SYSC_REG_HWFR 0x0000000c #define SYSC_REG_HWFR 0x0000000c
/* [0x10]: REG Timer Control Register */ /* [0x10]: REG Hardware Info Register */
#define SYSC_REG_TCR 0x00000010 #define SYSC_REG_HWIR 0x00000010
/* [0x14]: REG Timer Counter Value Register */ /* [0x14]: REG Timer Control Register */
#define SYSC_REG_TVR 0x00000014 #define SYSC_REG_TCR 0x00000014
/* [0x18]: REG User Diag: version register */ /* [0x18]: REG Timer Counter Value Register */
#define SYSC_REG_DIAG_INFO 0x00000018 #define SYSC_REG_TVR 0x00000018
/* [0x1c]: REG User Diag: number of words */ /* [0x1c]: REG User Diag: version register */
#define SYSC_REG_DIAG_NW 0x0000001c #define SYSC_REG_DIAG_INFO 0x0000001c
/* [0x20]: REG User Diag: Control Register */ /* [0x20]: REG User Diag: number of words */
#define SYSC_REG_DIAG_CR 0x00000020 #define SYSC_REG_DIAG_NW 0x00000020
/* [0x24]: REG User Diag: data to read/write */ /* [0x24]: REG User Diag: Control Register */
#define SYSC_REG_DIAG_DAT 0x00000024 #define SYSC_REG_DIAG_CR 0x00000024
/* [0x28]: REG WRPC Diag: ctrl */ /* [0x28]: REG User Diag: data to read/write */
#define SYSC_REG_WDIAG_CTRL 0x00000028 #define SYSC_REG_DIAG_DAT 0x00000028
/* [0x2c]: REG WRPC Diag: servo status */ /* [0x2c]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_SSTAT 0x0000002c #define SYSC_REG_WDIAG_CTRL 0x0000002c
/* [0x30]: REG WRPC Diag: Port status */ /* [0x30]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_PSTAT 0x00000030 #define SYSC_REG_WDIAG_SSTAT 0x00000030
/* [0x34]: REG WRPC Diag: PTP state */ /* [0x34]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PTPSTAT 0x00000034 #define SYSC_REG_WDIAG_PSTAT 0x00000034
/* [0x38]: REG WRPC Diag: AUX state */ /* [0x38]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_ASTAT 0x00000038 #define SYSC_REG_WDIAG_PTPSTAT 0x00000038
/* [0x3c]: REG WRPC Diag: Tx PTP Frame cnts */ /* [0x3c]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_TXFCNT 0x0000003c #define SYSC_REG_WDIAG_ASTAT 0x0000003c
/* [0x40]: REG WRPC Diag: Rx PTP Frame cnts */ /* [0x40]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000040 #define SYSC_REG_WDIAG_TXFCNT 0x00000040
/* [0x44]: REG WRPC Diag:local time [msb of s] */ /* [0x44]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_SEC_MSB 0x00000044 #define SYSC_REG_WDIAG_RXFCNT 0x00000044
/* [0x48]: REG WRPC Diag: local time [lsb of s] */ /* [0x48]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x00000048 #define SYSC_REG_WDIAG_SEC_MSB 0x00000048
/* [0x4c]: REG WRPC Diag: local time [ns] */ /* [0x4c]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_NS 0x0000004c #define SYSC_REG_WDIAG_SEC_LSB 0x0000004c
/* [0x50]: REG WRPC Diag: Round trip (mu) [msb of ps] */ /* [0x50]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000050 #define SYSC_REG_WDIAG_NS 0x00000050
/* [0x54]: REG WRPC Diag: Round trip (mu) [lsb of ps] */ /* [0x54]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x00000054 #define SYSC_REG_WDIAG_MU_MSB 0x00000054
/* [0x58]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */ /* [0x58]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x00000058 #define SYSC_REG_WDIAG_MU_LSB 0x00000058
/* [0x5c]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */ /* [0x5c]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x0000005c #define SYSC_REG_WDIAG_DMS_MSB 0x0000005c
/* [0x60]: REG WRPC Diag: Total link asymmetry [ps] */ /* [0x60]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000060 #define SYSC_REG_WDIAG_DMS_LSB 0x00000060
/* [0x64]: REG WRPC Diag: Clock offset (cko) [ps] */ /* [0x64]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_CKO 0x00000064 #define SYSC_REG_WDIAG_ASYM 0x00000064
/* [0x68]: REG WRPC Diag: Phase setpoint (setp) [ps] */ /* [0x68]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_SETP 0x00000068 #define SYSC_REG_WDIAG_CKO 0x00000068
/* [0x6c]: REG WRPC Diag: Update counter (ucnt) */ /* [0x6c]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_UCNT 0x0000006c #define SYSC_REG_WDIAG_SETP 0x0000006c
/* [0x70]: REG WRPC Diag: Board temperature [C degree] */ /* [0x70]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_TEMP 0x00000070 #define SYSC_REG_WDIAG_UCNT 0x00000070
/* [0x74]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000074
#endif #endif
...@@ -49,6 +49,7 @@ struct SYSCON_WB { ...@@ -49,6 +49,7 @@ struct SYSCON_WB {
uint32_t GPSR; /*GPIO Set/Readback Register */ uint32_t GPSR; /*GPIO Set/Readback Register */
uint32_t GPCR; /*GPIO Clear Register */ uint32_t GPCR; /*GPIO Clear Register */
uint32_t HWFR; /*Hardware Feature Register */ uint32_t HWFR; /*Hardware Feature Register */
uint32_t HWIR; /*Hardware Info Register */
uint32_t TCR; /*Timer Control Register */ uint32_t TCR; /*Timer Control Register */
uint32_t TVR; /*Timer Counter Value Register */ uint32_t TVR; /*Timer Counter Value Register */
uint32_t DIAG_INFO; uint32_t DIAG_INFO;
...@@ -124,6 +125,9 @@ static inline int sysc_get_memsize(void) ...@@ -124,6 +125,9 @@ static inline int sysc_get_memsize(void)
return (SYSC_HWFR_MEMSIZE_R(syscon->HWFR) + 1) * 16; return (SYSC_HWFR_MEMSIZE_R(syscon->HWFR) + 1) * 16;
} }
#define HW_NAME_LENGTH 5 /* 4 letters + '\0' */
void get_hw_name(char *str);
#define DIAG_RW_BANK 0 #define DIAG_RW_BANK 0
#define DIAG_RO_BANK 1 #define DIAG_RO_BANK 1
void diag_read_info(uint32_t *id, uint32_t *ver, uint32_t *nrw, uint32_t *nro); void diag_read_info(uint32_t *id, uint32_t *ver, uint32_t *nrw, uint32_t *nro);
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include "softpll_ng.h" #include "softpll_ng.h"
#include "temperature.h" #include "temperature.h"
#include "sfp.h" #include "sfp.h"
#include "syscon.h"
#include "storage.h" #include "storage.h"
...@@ -220,8 +221,7 @@ static uint32_t aux_diag_reg_rw_num; ...@@ -220,8 +221,7 @@ static uint32_t aux_diag_reg_rw_num;
extern struct pp_instance ppi_static; extern struct pp_instance ppi_static;
static struct wr_servo_state *wr_s_state; static struct wr_servo_state *wr_s_state;
#define SNMP_HW_TYPE_LEN 32 extern char wrc_hw_name[HW_NAME_LENGTH];
char snmp_hw_type[SNMP_HW_TYPE_LEN] = CONFIG_SNMP_HW_TYPE;
/* __DATE__ and __TIME__ is already stored in struct spll_stats stats, but /* __DATE__ and __TIME__ is already stored in struct spll_stats stats, but
* redefining it here makes code smaller than concatenate existing one */ * redefining it here makes code smaller than concatenate existing one */
static char *snmp_build_date = __DATE__ " " __TIME__; static char *snmp_build_date = __DATE__ " " __TIME__;
...@@ -351,7 +351,7 @@ static uint8_t oid_wrpcSfpAlpha[] = {5}; ...@@ -351,7 +351,7 @@ static uint8_t oid_wrpcSfpAlpha[] = {5};
OIDs */ OIDs */
/* wrpcVersionGroup */ /* wrpcVersionGroup */
static struct snmp_oid oid_array_wrpcVersionGroup[] = { static struct snmp_oid oid_array_wrpcVersionGroup[] = {
OID_FIELD_VAR( oid_wrpcVersionHwType, get_p, NO_SET, ASN_OCTET_STR, &snmp_hw_type), OID_FIELD_VAR( oid_wrpcVersionHwType, get_p, NO_SET, ASN_OCTET_STR, &wrc_hw_name),
OID_FIELD_VAR( oid_wrpcVersionSwVersion, get_pp, NO_SET, ASN_OCTET_STR, &build_revision), OID_FIELD_VAR( oid_wrpcVersionSwVersion, get_pp, NO_SET, ASN_OCTET_STR, &build_revision),
OID_FIELD_VAR( oid_wrpcVersionSwBuildBy, get_pp, NO_SET, ASN_OCTET_STR, &build_by), OID_FIELD_VAR( oid_wrpcVersionSwBuildBy, get_pp, NO_SET, ASN_OCTET_STR, &build_by),
OID_FIELD_VAR( oid_wrpcVersionSwBuildDate, get_pp, NO_SET, ASN_OCTET_STR, &snmp_build_date), OID_FIELD_VAR( oid_wrpcVersionSwBuildDate, get_pp, NO_SET, ASN_OCTET_STR, &snmp_build_date),
......
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
int wrc_ui_mode = UI_SHELL_MODE; int wrc_ui_mode = UI_SHELL_MODE;
int wrc_ui_refperiod = TICS_PER_SECOND; /* 1 sec */ int wrc_ui_refperiod = TICS_PER_SECOND; /* 1 sec */
int wrc_phase_tracking = 1; int wrc_phase_tracking = 1;
char wrc_hw_name[HW_NAME_LENGTH];
uint32_t cal_phase_transition = 2389; uint32_t cal_phase_transition = 2389;
...@@ -54,6 +55,7 @@ static void wrc_initialize(void) ...@@ -54,6 +55,7 @@ static void wrc_initialize(void)
pp_printf("WR Core: starting up...\n"); pp_printf("WR Core: starting up...\n");
timer_init(1); timer_init(1);
get_hw_name(wrc_hw_name);
wrpc_w1_init(); wrpc_w1_init();
wrpc_w1_bus.detail = ONEWIRE_PORT; wrpc_w1_bus.detail = ONEWIRE_PORT;
w1_scan_bus(&wrpc_w1_bus); w1_scan_bus(&wrpc_w1_bus);
......
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