Skip to content

S
Software for White Rabbit PTP Core
Commit 98d30695 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

dev: follow up Endpoint's MDIO memmap changes in the endpoint driver.

parent 150c4d4b
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 248 additions and 436 deletions
dev/endpoint.c
View file @ 98d30695
......@@ -20,7 +20,7 @@
#include "ppsi/lib.h"
#include <hw/endpoint_regs.h>
#include <hw/endpoint_mdio.h>
#include <hw/ep_mdio_regs.h>
#include <wrc_global.h>
......@@ -31,14 +31,22 @@
/* functions for accessing PCS (MDIO) registers */
uint16_t ep_pcs_read(struct wr_endpoint_device *dev, int location)
{
ep_write( dev, EP_REG_MDIO_CR, EP_MDIO_CR_ADDR_W(location >> 2) );
ep_write(dev, EP_REG_MDIO_ASR, ((location >> 10) & 0xff) << EP_MDIO_ASR_PHYAD_SHIFT);
ep_write(dev, EP_REG_MDIO_CR,
(((location >> 2) & 0xff) << EP_MDIO_CR_ADDR_SHIFT) );
while (( ep_read(dev, EP_REG_MDIO_ASR) & EP_MDIO_ASR_READY) == 0) ;
return EP_MDIO_ASR_RDATA_R(ep_read(dev, EP_REG_MDIO_ASR)) & 0xffff;
uint32_t rv = EP_MDIO_ASR_RDATA_R(ep_read(dev, EP_REG_MDIO_ASR)) & 0xffff;
return rv;
}
void ep_pcs_write(struct wr_endpoint_device *dev, int location, int value)
{
ep_write(dev, EP_REG_MDIO_CR, EP_MDIO_CR_ADDR_W(location >> 2)
ep_write(dev, EP_REG_MDIO_ASR, ((location >> 10) & 0xff) << EP_MDIO_ASR_PHYAD_SHIFT);
ep_write(dev, EP_REG_MDIO_CR,
(((location >> 2) & 0xff) << EP_MDIO_CR_ADDR_SHIFT)
| EP_MDIO_CR_DATA_W(value)
| EP_MDIO_CR_RW );
......@@ -115,22 +123,23 @@ void ep_reset_phy(struct wr_endpoint_device* dev)
uint32_t mcr;
/* Reset the GTP Transceiver - it's important to do the GTP phase alignment every time
we start up the software, otherwise the calibration RX/TX deltas may not be correct */
ep_pcs_write(dev, MDIO_REG_MCR, MDIO_MCR_PDOWN); /* reset the PHY */
ep_pcs_write(dev, EP_MDIO_MCR, EP_MDIO_MCR_PDOWN); /* reset the PHY */
pp_printf("Running long PHY reset...\n");
phy_dbg("Running long PHY reset...\n");
timer_delay_ms(1000);
pp_printf("PHY reset complete\n");
ep_pcs_write(dev, MDIO_REG_MCR, MDIO_MCR_RESET); /* reset the PHY */
ep_pcs_write(dev, MDIO_REG_MCR, 0); /* reset the PHY */
phy_dbg("PHY reset complete\n");
ep_pcs_write(dev, EP_MDIO_MCR, EP_MDIO_MCR_RESET); /* reset the PHY */
ep_pcs_write(dev, EP_MDIO_MCR, 0); /* reset the PHY */
/* Don't advertise anything - we don't want flow control */
ep_pcs_write(dev, MDIO_REG_ADVERTISE, 0);
ep_pcs_write(dev, EP_MDIO_ADVERTISE, 0);
mcr = MDIO_MCR_SPEED1000_MASK | MDIO_MCR_FULLDPLX_MASK;
mcr = EP_MDIO_MCR_SPEED1000 | EP_MDIO_MCR_FULLDPLX;
if (dev->flags & EP_DEV_AUTONEG_ENABLED)
mcr |= MDIO_MCR_ANENABLE | MDIO_MCR_ANRESTART;
mcr |= EP_MDIO_MCR_ANENABLE | EP_MDIO_MCR_ANRESTART;
ep_pcs_write(dev, MDIO_REG_MCR, mcr);
ep_pcs_write(dev, EP_MDIO_MCR, mcr);
ep_pcs_write(dev, EP_MDIO_WR_SPEC, 0);
}
/* Enables/disables transmission and reception. When autoneg is set to 1,
......@@ -168,17 +177,19 @@ int ep_enable(struct wr_endpoint_device* dev, int enabled, int autoneg)
and stores the Link Partner Ability (LPA) autonegotiation register at *lpa */
int ep_link_up(struct wr_endpoint_device* dev, uint16_t * lpa)
{
uint16_t flags = MDIO_MSR_LSTATUS;
uint16_t flags = EP_MDIO_MSR_LSTATUS;
volatile uint16_t msr;
if (dev->flags & EP_DEV_AUTONEG_ENABLED)
flags |= MDIO_MSR_ANEGCOMPLETE;
flags |= EP_MDIO_MSR_ANEGCOMPLETE;
msr = ep_pcs_read(dev, MDIO_REG_MSR);
msr = ep_pcs_read(dev, MDIO_REG_MSR); /* Read this flag twice to make sure the status is updated */
msr = ep_pcs_read(dev, EP_MDIO_MSR);
msr = ep_pcs_read(dev, EP_MDIO_MSR); /* Read this flag twice to make sure the status is updated */
//pp_printf("MSR %x\n", msr);
if (lpa)
*lpa = ep_pcs_read(dev, MDIO_REG_LPA);
*lpa = ep_pcs_read(dev, EP_MDIO_LPA);
return (msr & flags) == flags ? 1 : 0;
}
......@@ -186,7 +197,7 @@ int ep_link_up(struct wr_endpoint_device* dev, uint16_t * lpa)
int ep_get_bitslide(struct wr_endpoint_device* dev)
{
return PICOS_PER_SERIAL_BIT *
MDIO_WR_SPEC_BSLIDE_R(ep_pcs_read(dev, MDIO_REG_WR_SPEC));
(( ep_pcs_read(dev, EP_MDIO_WR_SPEC) & EP_MDIO_WR_SPEC_BSLIDE_MASK) >> EP_MDIO_WR_SPEC_BSLIDE_SHIFT);
}
/* Returns the TX/RX latencies. They are valid only when the link is up. */
......@@ -208,13 +219,13 @@ int ep_sfp_enable(struct wr_endpoint_device* dev, int ena)
{
uint32_t val;
val = ep_pcs_read(dev, MDIO_REG_ECTRL);
val = ep_pcs_read(dev, EP_MDIO_ECTRL);
if(ena)
val &= (~MDIO_ECTRL_SFP_TX_DISABLE);
val &= (~EP_MDIO_ECTRL_SFP_TX_DISABLE);
else
val |= MDIO_ECTRL_SFP_TX_DISABLE;
ep_pcs_write(dev, MDIO_REG_ECTRL, val);
val |= EP_MDIO_ECTRL_SFP_TX_DISABLE;
ep_pcs_write(dev, EP_MDIO_ECTRL, val);
return 0;
}
include/hw/endpoint_mdio.h deleted 100644 → 0
View file @ 150c4d4b
This diff is collapsed.
include/hw/ep_mdio_regs.h 0 → 100644
View file @ 98d30695
#ifndef __CHEBY__EP_MDIO__H__
#define __CHEBY__EP_MDIO__H__
#define EP_MDIO_SIZE 16384 /* 0x4000 = 16KB */
/* MDIO Control Register */
#define EP_MDIO_MCR 0x0UL
#define EP_MDIO_MCR_RESV_MASK 0x1fUL
#define EP_MDIO_MCR_RESV_SHIFT 0
#define EP_MDIO_MCR_UNI_EN 0x20UL
#define EP_MDIO_MCR_SPEED1000 0x40UL
#define EP_MDIO_MCR_CTST 0x80UL
#define EP_MDIO_MCR_FULLDPLX 0x100UL
#define EP_MDIO_MCR_ANRESTART 0x200UL
#define EP_MDIO_MCR_ISOLATE 0x400UL
#define EP_MDIO_MCR_PDOWN 0x800UL
#define EP_MDIO_MCR_ANENABLE 0x1000UL
#define EP_MDIO_MCR_SPEED100 0x2000UL
#define EP_MDIO_MCR_LOOPBACK 0x4000UL
#define EP_MDIO_MCR_RESET 0x8000UL
/* MDIO Status Register */
#define EP_MDIO_MSR 0x4UL
#define EP_MDIO_MSR_ERCAP 0x1UL
#define EP_MDIO_MSR_JCD 0x2UL
#define EP_MDIO_MSR_LSTATUS 0x4UL
#define EP_MDIO_MSR_ANEGCAPABLE 0x8UL
#define EP_MDIO_MSR_RFAULT 0x10UL
#define EP_MDIO_MSR_ANEGCOMPLETE 0x20UL
#define EP_MDIO_MSR_MFSUPPRESS 0x40UL
#define EP_MDIO_MSR_UNIDIRABLE 0x80UL
#define EP_MDIO_MSR_ESTATEN 0x100UL
#define EP_MDIO_MSR_100HALF2 0x200UL
#define EP_MDIO_MSR_100FULL2 0x400UL
#define EP_MDIO_MSR_10HALF 0x800UL
#define EP_MDIO_MSR_10FULL 0x1000UL
#define EP_MDIO_MSR_100HALF 0x2000UL
#define EP_MDIO_MSR_100FULL 0x4000UL
#define EP_MDIO_MSR_100BASE4 0x8000UL
/* MDIO PHY Identification Register 1 */
#define EP_MDIO_PHYSID1 0x8UL
#define EP_MDIO_PHYSID1_OUI_MASK 0xffffUL
#define EP_MDIO_PHYSID1_OUI_SHIFT 0
/* MDIO PHY Identification Register 2 */
#define EP_MDIO_PHYSID2 0xcUL
#define EP_MDIO_PHYSID2_REV_NUM_MASK 0xfUL
#define EP_MDIO_PHYSID2_REV_NUM_SHIFT 0
#define EP_MDIO_PHYSID2_MMNUM_MASK 0x3f0UL
#define EP_MDIO_PHYSID2_MMNUM_SHIFT 4
#define EP_MDIO_PHYSID2_OUI_MASK 0xfc00UL
#define EP_MDIO_PHYSID2_OUI_SHIFT 10
/* MDIO Auto-Negotiation Advertisement Register */
#define EP_MDIO_ADVERTISE 0x10UL
#define EP_MDIO_ADVERTISE_RSVD3_MASK 0x1fUL
#define EP_MDIO_ADVERTISE_RSVD3_SHIFT 0
#define EP_MDIO_ADVERTISE_FULL 0x20UL
#define EP_MDIO_ADVERTISE_HALF 0x40UL
#define EP_MDIO_ADVERTISE_PAUSE_MASK 0x180UL
#define EP_MDIO_ADVERTISE_PAUSE_SHIFT 7
#define EP_MDIO_ADVERTISE_RSVD2_MASK 0xe00UL
#define EP_MDIO_ADVERTISE_RSVD2_SHIFT 9
#define EP_MDIO_ADVERTISE_RFAULT_MASK 0x3000UL
#define EP_MDIO_ADVERTISE_RFAULT_SHIFT 12
#define EP_MDIO_ADVERTISE_RSVD1 0x4000UL
#define EP_MDIO_ADVERTISE_NPAGE 0x8000UL
/* MDIO Auto-Negotiation Link Partner Ability Register */
#define EP_MDIO_LPA 0x14UL
#define EP_MDIO_LPA_RSVD3_MASK 0x1fUL
#define EP_MDIO_LPA_RSVD3_SHIFT 0
#define EP_MDIO_LPA_FULL 0x20UL
#define EP_MDIO_LPA_HALF 0x40UL
#define EP_MDIO_LPA_PAUSE_MASK 0x180UL
#define EP_MDIO_LPA_PAUSE_SHIFT 7
#define EP_MDIO_LPA_RSVD2_MASK 0xe00UL
#define EP_MDIO_LPA_RSVD2_SHIFT 9
#define EP_MDIO_LPA_RFAULT_MASK 0x3000UL
#define EP_MDIO_LPA_RFAULT_SHIFT 12
#define EP_MDIO_LPA_LPACK 0x4000UL
#define EP_MDIO_LPA_NPAGE 0x8000UL
/* MDIO Auto-Negotiation Expansion Register */
#define EP_MDIO_EXPANSION 0x18UL
#define EP_MDIO_EXPANSION_RSVD1 0x1UL
#define EP_MDIO_EXPANSION_LWCP 0x2UL
#define EP_MDIO_EXPANSION_ENABLENPAGE 0x4UL
#define EP_MDIO_EXPANSION_RSVD2_MASK 0xfff8UL
#define EP_MDIO_EXPANSION_RSVD2_SHIFT 3
/* MDIO Extended Status Register */
#define EP_MDIO_ESTATUS 0x3cUL
#define EP_MDIO_ESTATUS_RSVD1_MASK 0xfffUL
#define EP_MDIO_ESTATUS_RSVD1_SHIFT 0
#define EP_MDIO_ESTATUS_1000_THALF 0x1000UL
#define EP_MDIO_ESTATUS_1000_TFULL 0x2000UL
#define EP_MDIO_ESTATUS_1000_XHALF 0x4000UL
#define EP_MDIO_ESTATUS_1000_XFULL 0x8000UL
/* White Rabbit-specific Configuration Register */
#define EP_MDIO_WR_SPEC 0x40UL
#define EP_MDIO_WR_SPEC_TX_CAL 0x1UL
#define EP_MDIO_WR_SPEC_RX_CAL_STAT 0x2UL
#define EP_MDIO_WR_SPEC_CAL_CRST 0x4UL
#define EP_MDIO_WR_SPEC_BSLIDE_MASK 0x1f0UL
#define EP_MDIO_WR_SPEC_BSLIDE_SHIFT 4
/* MDIO Extended Control Register */
#define EP_MDIO_ECTRL 0x44UL
#define EP_MDIO_ECTRL_LPBCK_VEC_MASK 0x7UL
#define EP_MDIO_ECTRL_LPBCK_VEC_SHIFT 0
#define EP_MDIO_ECTRL_SFP_TX_FAULT 0x8UL
#define EP_MDIO_ECTRL_SFP_LOSS 0x10UL
#define EP_MDIO_ECTRL_SFP_TX_DISABLE 0x20UL
#define EP_MDIO_ECTRL_TX_PRBS_SEL_MASK 0x700UL
#define EP_MDIO_ECTRL_TX_PRBS_SEL_SHIFT 8
/* Custom PHY-specific registers. */
#define EP_MDIO_PHY_SPECIFIC_REGS 0x2000UL
#define ADDR_MASK_EP_MDIO_PHY_SPECIFIC_REGS 0x2000UL
#define EP_MDIO_PHY_SPECIFIC_REGS_SIZE 8192 /* 0x2000 = 8KB */
struct ep_mdio {
/* [0x0]: REG (rw) MDIO Control Register */
uint32_t MCR;
/* [0x4]: REG (ro) MDIO Status Register */
uint32_t MSR;
/* [0x8]: REG (ro) MDIO PHY Identification Register 1 */
uint32_t PHYSID1;
/* [0xc]: REG (ro) MDIO PHY Identification Register 2 */
uint32_t PHYSID2;
/* [0x10]: REG (rw) MDIO Auto-Negotiation Advertisement Register */
uint32_t ADVERTISE;
/* [0x14]: REG (ro) MDIO Auto-Negotiation Link Partner Ability Register */
uint32_t LPA;
/* [0x18]: REG (ro) MDIO Auto-Negotiation Expansion Register */
uint32_t EXPANSION;
/* padding to: 15 words */
uint32_t __padding_0[8];
/* [0x3c]: REG (ro) MDIO Extended Status Register */
uint32_t ESTATUS;
/* [0x40]: REG (rw) White Rabbit-specific Configuration Register */
uint32_t WR_SPEC;
/* [0x44]: REG (rw) MDIO Extended Control Register */
uint32_t ECTRL;
/* padding to: 2048 words */
uint32_t __padding_1[2030];
/* [0x2000]: SUBMAP Custom PHY-specific registers. */
uint32_t phy_specific_regs[2048];
};
#endif /* __CHEBY__EP_MDIO__H__ */
include/hw/lpdc_mdio_regs.h 0 → 100644
View file @ 98d30695
#ifndef __CHEBY__LPDC_MDIO__H__
#define __CHEBY__LPDC_MDIO__H__
#define LPDC_MDIO_SIZE 8192 /* 0x2000 = 8KB */
/* Low Phase Drift Calibration Control Register */
#define LPDC_MDIO_CTRL 0x0UL
#define LPDC_MDIO_CTRL_TX_SW_RESET 0x1UL
#define LPDC_MDIO_CTRL_TX_ENABLE 0x2UL
#define LPDC_MDIO_CTRL_RX_ENABLE 0x4UL
#define LPDC_MDIO_CTRL_RX_SW_RESET 0x8UL
#define LPDC_MDIO_CTRL_QPLL_SW_RESET 0x10UL
#define LPDC_MDIO_CTRL_TXUSRPLL_RESET 0x20UL
#define LPDC_MDIO_CTRL_COMMA_TARGET_POS_MASK 0x3fc0UL
#define LPDC_MDIO_CTRL_COMMA_TARGET_POS_SHIFT 6
#define LPDC_MDIO_CTRL_DMTD_CLK_SEL_MASK 0xc000UL
#define LPDC_MDIO_CTRL_DMTD_CLK_SEL_SHIFT 14
/* Low Phase Drift Calibration Status Register */
#define LPDC_MDIO_STAT 0x4UL
#define LPDC_MDIO_STAT_QPLL_LOCKED 0x1UL
#define LPDC_MDIO_STAT_LINK_UP 0x2UL
#define LPDC_MDIO_STAT_LINK_ALIGNED 0x4UL
#define LPDC_MDIO_STAT_TX_RST_DONE 0x8UL
#define LPDC_MDIO_STAT_TXUSRPLL_LOCKED 0x10UL
#define LPDC_MDIO_STAT_RX_RST_DONE 0x20UL
#define LPDC_MDIO_STAT_COMMA_CURRENT_POS_MASK 0x7f80UL
#define LPDC_MDIO_STAT_COMMA_CURRENT_POS_SHIFT 7
/* Xilinx DRP registers, specific to the transceiver */
#define LPDC_MDIO_DRP_REGS 0x1000UL
#define ADDR_MASK_LPDC_MDIO_DRP_REGS 0x1000UL
#define LPDC_MDIO_DRP_REGS_SIZE 4096 /* 0x1000 = 4KB */
struct lpdc_mdio {
/* [0x0]: REG (rw) Low Phase Drift Calibration Control Register */
uint32_t CTRL;
/* [0x4]: REG (ro) Low Phase Drift Calibration Status Register */
uint32_t STAT;
/* padding to: 1024 words */
uint32_t __padding_0[1022];
/* [0x1000]: SUBMAP Xilinx DRP registers, specific to the transceiver */
uint32_t drp_regs[1024];
};
#endif /* __CHEBY__LPDC_MDIO__H__ */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment