added new headers

8eaac2fc · Tomasz Wlostowski · e42c3438 · 8eaac2fc · 8eaac2fc
Commit 8eaac2fc authored Apr 08, 2011 by Tomasz Wlostowski
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softpll_regs.h include/hw/softpll_regs.h +107 -0

irq.h include/irq.h +10 -0

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--- a/include/hw/softpll_regs.h
+++ b/include/hw/softpll_regs.h
+/*
+  Register definitions for slave core: WR Softcore PLL
+
+  * File           : softpll_regs.h
+  * Author         : auto-generated by wbgen2 from wr_softpll.wb
+  * Created        : Fri Apr  8 20:09:44 2011
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_softpll.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WR_SOFTPLL_WB
+#define __WBGEN2_REGDEFS_WR_SOFTPLL_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: SPLL Control/Status Register */
+
+/* definitions for field: Tagger enable in reg: SPLL Control/Status Register */
+#define SPLL_CSR_TAG_EN_MASK                  WBGEN2_GEN_MASK(0, 4)
+#define SPLL_CSR_TAG_EN_SHIFT                 0
+#define SPLL_CSR_TAG_EN_W(value)              WBGEN2_GEN_WRITE(value, 0, 4)
+#define SPLL_CSR_TAG_EN_R(reg)                WBGEN2_GEN_READ(reg, 0, 4)
+
+/* definitions for field: Tag ready in reg: SPLL Control/Status Register */
+#define SPLL_CSR_TAG_RDY_MASK                 WBGEN2_GEN_MASK(4, 4)
+#define SPLL_CSR_TAG_RDY_SHIFT                4
+#define SPLL_CSR_TAG_RDY_W(value)             WBGEN2_GEN_WRITE(value, 4, 4)
+#define SPLL_CSR_TAG_RDY_R(reg)               WBGEN2_GEN_READ(reg, 4, 4)
+
+/* definitions for register: HPLL Tag */
+
+/* definitions for register: HPLL Period */
+
+/* definitions for register: DMPLL Tag ref */
+
+/* definitions for register: DMPLL Tag fb */
+
+/* definitions for register: HPLL DAC Output */
+
+/* definitions for register: DMPLL DAC Output */
+
+/* definitions for register: Interrupt disable register */
+
+/* definitions for field: Got a tag in reg: Interrupt disable register */
+#define SPLL_EIC_IDR_TAG                      WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for register: Interrupt enable register */
+
+/* definitions for field: Got a tag in reg: Interrupt enable register */
+#define SPLL_EIC_IER_TAG                      WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for register: Interrupt mask register */
+
+/* definitions for field: Got a tag in reg: Interrupt mask register */
+#define SPLL_EIC_IMR_TAG                      WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for register: Interrupt status register */
+
+/* definitions for field: Got a tag in reg: Interrupt status register */
+#define SPLL_EIC_ISR_TAG                      WBGEN2_GEN_MASK(0, 1)
+
+PACKED struct SPLL_WB {
+  /* [0x0]: REG SPLL Control/Status Register */
+  uint32_t CSR;
+  /* [0x4]: REG HPLL Tag */
+  uint32_t TAG_HPLL;
+  /* [0x8]: REG HPLL Period */
+  uint32_t PER_HPLL;
+  /* [0xc]: REG DMPLL Tag ref */
+  uint32_t TAG_REF;
+  /* [0x10]: REG DMPLL Tag fb */
+  uint32_t TAG_FB;
+  /* [0x14]: REG HPLL DAC Output */
+  uint32_t DAC_HPLL;
+  /* [0x18]: REG DMPLL DAC Output */
+  uint32_t DAC_DMPLL;
+  /* padding to: 8 words */
+  uint32_t __padding_0[1];
+  /* [0x20]: REG Interrupt disable register */
+  uint32_t EIC_IDR;
+  /* [0x24]: REG Interrupt enable register */
+  uint32_t EIC_IER;
+  /* [0x28]: REG Interrupt mask register */
+  uint32_t EIC_IMR;
+  /* [0x2c]: REG Interrupt status register */
+  uint32_t EIC_ISR;
+};
+
+#endif
--- a/include/irq.h
+++ b/include/irq.h
+#ifndef __IRQ_H
+#define __IRQ_H
+
+static inline void clear_irq()
+{
+  unsigned int val = 1;
+  asm volatile ("wcsr ip, %0"::"r"(val));
+}
+
+#endif