Commit 6a71c8dd authored by Peter Jansweijer's avatar Peter Jansweijer

add wb_gpio_create

parent 2937f091
Pipeline #293 failed with stages
in 9 seconds
......@@ -39,6 +39,10 @@ void spec7_set_pll_wr_mode(int pll_wr_mode)
int spec7_init()
{
/* most of the I/Os of the slow peripherals (i2c, spi) are bitbanged. First, let's
initialize the GPIO controller they're connected to */
wb_gpio_create( &board.gpio_aux, BASE_GPIO );
// Use free running dmtd clock for bootstrapping
gen_gpio_out( &pin_pll_clk_sel, 0);
......
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