softpll: prevent AUX clock FSM from getting stuck when the first locking attempt…

softpll: prevent AUX clock FSM from getting stuck when the first locking attempt is unsuccessful. Also hack to fix the frequency/phase regulation mode threshold - to be exposed through api

softpll: prevent AUX clock FSM from getting stuck when the first locking attempt…
softpll: prevent AUX clock FSM from getting stuck when the first locking attempt is unsuccessful. Also hack to fix the frequency/phase regulation mode threshold - to be exposed through api
689fb434 · Tomasz Wlostowski · 6ac8a21d · 689fb434 · 689fb434 · 689fb434
Commit 689fb434 authored Oct 14, 2021 by Tomasz Wlostowski
Hide whitespace changes
Inline Side-by-side

Showing with 15 additions and 10 deletions

softpll_ng.c softpll/softpll_ng.c +13 -8

softpll_ng.h softpll/softpll_ng.h +1 -1

spll_main.c softpll/spll_main.c +1 -1

No files found.
--- a/softpll/softpll_ng.c
+++ b/softpll/softpll_ng.c
@@ -422,14 +422,14 @@ void spll_shutdown()
 	SPLL->EIC_IDR = 1;
 }

-void spll_start_channel(int channel)
+int spll_start_channel(int channel)
 {
 	struct softpll_state *s = (struct softpll_state *) &softpll;

 	if (s->seq_state != SEQ_READY || !channel) {
 		pll_verbose("Can't start channel %d, the PLL is not ready\n",
 			  channel);
-		return;
+		return -1;
 	}

 	struct spll_main_state *m = &s->aux[channel - 1].pll.dmtd;
@@ -437,8 +437,11 @@ void spll_start_channel(int channel)
 	m->div_cnt = 0;
 	m->div_ref = s->aux[channel - 1].div_ref;
 	m->div_fb = s->aux[channel - 1].div_fb;
-
+	
 	mpll_start(&s->aux[channel - 1].pll.dmtd);
+	m->frequency_lock_threshold = 100; // HACK: make this programmable (we need higher threshold for the main VCO than for the AUXes, esp. silabs)
+
+	return 0;
 }

 void spll_stop_channel(int channel)
@@ -568,9 +571,9 @@ void spll_show_stats()

 		pp_printf("softpll: AUX%d [ratio %d/%d = %d Hz]: ph %d seq %d en %d lock %d samples %d nref %d nout %d ERR=%d Y=%d\n", 
 				ch-1,
-				s->pll.dmtd.div_fb,
-				s->pll.dmtd.div_ref,
-				REF_CLOCK_FREQ_HZ * s->pll.dmtd.div_fb / s->pll.dmtd.div_ref,
+				s->div_fb,
+				s->div_ref,
+				REF_CLOCK_FREQ_HZ * s->div_fb / s->div_ref,
 				s->phase_value,
 				s->seq_state,
 				s->pll.dmtd.enabled,
@@ -638,8 +641,10 @@ static int spll_update_aux_clocks(void)
 					if( s->mode == SPLL_AUX_MODE_SLAVE )
 					{
 						pll_verbose("softpll: enabled slave aux channel %d\n", ch);
-						spll_start_channel(ch);
-						s->seq_state = AUX_LOCK_PLL;
+						if( !spll_start_channel(ch) )
+						{
+							s->seq_state = AUX_LOCK_PLL;
+						}
 						done_sth++;
 					}
 					else if ( s->mode == SPLL_AUX_MODE_PHASE_MONITOR )

--- a/softpll/softpll_ng.h
+++ b/softpll/softpll_ng.h
@@ -78,7 +78,7 @@ void spll_shutdown(void);
 void spll_get_num_channels(int *n_ref, int *n_out);

 /* Starts locking output channel (out_channel) */
-void spll_start_channel(int out_channel);
+int spll_start_channel(int out_channel);

 /* Stops locking output channel (out_channel) */
 void spll_stop_channel(int out_channel);

--- a/softpll/spll_main.c
+++ b/softpll/spll_main.c
@@ -50,7 +50,7 @@ void mpll_init(struct spll_main_state *s, int id_ref,
 #endif
 	s->enabled = 0;

-	s->frequency_lock_threshold = 100;
+	s->frequency_lock_threshold = 1000;

 	/* Freqency branch lock detection */
 	s->ld.threshold = 1200;