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Software for White Rabbit PTP Core
Commit 65333e73 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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softpll: add API for accessing debug buffer through wrpc-sw

parent ba214dc9
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Showing with 79 additions and 2 deletions
softpll/softpll_ng.c
View file @ 65333e73
......@@ -365,7 +365,25 @@ void spll_init(int mode, int slave_ref_channel, int flags)
/* Purge tag buffer */
while (!(SPLL->TRR_CSR & SPLL_TRR_CSR_EMPTY))
{
dummy = SPLL->TRR_R0;
(void) dummy;
}
/* Purge debug queue */
if ( SPLL->CSR & SPLL_CSR_DBG_SUPPORTED )
{
while (!(SPLL->DFR_HOST_CSR & SPLL_DFR_HOST_CSR_EMPTY))
{
dummy = SPLL->DFR_HOST_R0;
(void) dummy;
}
}
if(mode == SPLL_MODE_DISABLED)
return;
SPLL->EIC_IER = 1;
SPLL->OCER |= 1;
......@@ -747,3 +765,55 @@ void spll_set_gain_schedule( spll_gain_schedule_t* sch )
enable_irq();
}
void spll_debug_queue_purge(void)
{
int dummy;
while (!(SPLL->DFR_HOST_CSR & SPLL_DFR_HOST_CSR_EMPTY))
{
dummy = SPLL->DFR_HOST_R0;
(void) dummy;
}
}
int spll_get_debug_queue_samples( uint32_t *buf, int count, int undersample )
{
int cnt = count;
int pass = 1;
int und_cnt = 0;
int n_ents = 0;
if ( SPLL->DFR_HOST_CSR & SPLL_DFR_HOST_CSR_EMPTY )
return 0;
while(cnt > 0)
{
uint32_t v = SPLL->DFR_HOST_R0;
int tag = (v & DBG_TAG_MASK) >> DBG_TAG_SHIFT;
if(pass || tag == DBG_EVENT)
{
*buf++ = v;
n_ents ++;
}
if( v & 0x80000000 ) // last entry in the record
{
und_cnt++;
if (und_cnt == undersample)
{
und_cnt = 0;
pass = 1;
cnt--;
} else {
pass = 0;
}
}
}
return n_ents;
}
softpll/softpll_ng.h
View file @ 65333e73
......@@ -116,6 +116,9 @@ void spll_set_gain_schedule( spll_gain_schedule_t* sch );
void check_vco_frequencies(void);
void spll_set_ptracker_average_samples(int channel, int nsamples);
int spll_get_debug_queue_samples( uint32_t *buf, int size, int undersample );
void spll_debug_queue_purge(void);
/*
* Aux and main state:
* used to be in .c file, but we need it here for memory dumping
......
softpll/spll_debug.h
View file @ 65333e73
......@@ -26,9 +26,13 @@ integral/proportional gains on the response of the system.
#define DBG_EVENT 4
#define DBG_SAMPLE_ID 6
#define DBG_TAG_MASK 0xf0
#define DBG_TAG_SHIFT 4
#define DBG_EVENT 0x40
#define DBG_HELPER 0x20 /* Sample source: Helper PLL */
#define DBG_EXT 0x40 /* Sample source: External Reference PLL */
#define DBG_MAIN 0x0 /* ... : Main PLL */
#define DBG_EXT 0x10 /* Sample source: External Reference PLL */
#define DBG_MAIN 0x00 /* ... : Main PLL */
#define DBG_EVT_START 1 /* PLL has just started */
#define DBG_EVT_LOCKED 2 /* PLL has just become locked */
......
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