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Software for White Rabbit PTP Core
Commit 5ccade7c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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minic_fifo: removing legacy code, make it compile with new header and do nothing

parent 9fc08cfa
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Showing with 96 additions and 177 deletions
dev/minic.c
View file @ 5ccade7c
......@@ -49,7 +49,6 @@
rc = (raw) & 0xfffffff; \
fc = (raw >> 28) & 0xf;
static volatile uint32_t dma_tx_buf[MINIC_DMA_TX_BUF_SIZE / 4];
static volatile uint32_t dma_rx_buf[MINIC_DMA_RX_BUF_SIZE / 4];
struct wr_minic minic;
......@@ -64,108 +63,14 @@ static inline uint32_t minic_readl(uint32_t reg)
return *(volatile uint32_t *)(BASE_MINIC + reg);
}
/*
* uint32_t size - in bytes
*/
static uint8_t *minic_rx_memcpy(uint8_t * dst, uint8_t * src, uint32_t size)
{
uint32_t part;
//if src is outside the circular buffer, bring it back to the beginning
src = (uint8_t *)((uint32_t)minic.rx_base +
((uint32_t)src - (uint32_t) minic.rx_base)
% (minic.rx_size << 2));
if ((uint32_t)src + size <= (uint32_t)minic.rx_base
+ (minic.rx_size << 2))
return memcpy(dst, src, size);
part = (uint32_t)minic.rx_base + (minic.rx_size << 2) - (uint32_t)src;
memcpy(dst, src, part);
memcpy((void *)(dst + part), (void *)minic.rx_base, size - part);
return dst;
}
/*
* uint32_t size - in bytes
*/
static uint8_t *minic_rx_memset(uint8_t * mem, uint8_t c, uint32_t size)
{
uint32_t part;
uint32_t *src;
//if src is outside the circular buffer, bring it back to the beginning
src = (uint32_t *)((uint32_t)minic.rx_base +
((uint32_t) mem - (uint32_t) minic.rx_base)
% (minic.rx_size << 2));
if ((uint32_t) src + size <= (uint32_t) minic.rx_base
+ (minic.rx_size << 2))
return memset((void *)src, c, size);
part = (uint32_t) minic.rx_base + (minic.rx_size << 2) - (uint32_t) src;
memset(src, c, part);
memset((void *)minic.rx_base, c, size - part);
return (uint8_t *) src;
}
static void minic_new_rx_buffer(void)
{
minic_writel(MINIC_REG_MCR, 0);
minic.rx_base = dma_rx_buf;
minic.rx_size = MINIC_DMA_RX_BUF_SIZE / 4;
minic.rx_head = minic.rx_base;
minic_rx_memset((uint8_t *) minic.rx_base, 0x00, minic.rx_size << 2);
minic_writel(MINIC_REG_RX_ADDR, (uint32_t) minic.rx_base);
minic_writel(MINIC_REG_RX_SIZE, minic.rx_size);
//new buffer allocated, clear any old RX interrupts
minic_writel(MINIC_REG_EIC_ISR, MINIC_EIC_ISR_RX);
minic_writel(MINIC_REG_MCR, MINIC_MCR_RX_EN);
}
static void minic_rxbuf_free(uint32_t words)
{
minic_rx_memset((uint8_t *) minic.rx_head, 0x00, words << 2);
minic_writel(MINIC_REG_RX_AVAIL, words);
}
static void minic_new_tx_buffer(void)
{
minic.tx_base = dma_tx_buf;
minic.tx_size = MINIC_DMA_TX_BUF_SIZE >> 2;
minic.tx_head = minic.tx_base;
minic.tx_avail = minic.tx_size;
minic_writel(MINIC_REG_TX_ADDR, (uint32_t) minic.tx_base);
}
void minic_init()
{
uint32_t lo, hi;
minic_writel(MINIC_REG_EIC_IDR, MINIC_EIC_IDR_RX);
minic_writel(MINIC_REG_EIC_ISR, MINIC_EIC_ISR_RX);
minic.rx_base = dma_rx_buf;
minic.rx_size = sizeof(dma_rx_buf);
/* FIXME: now we have a temporary HW protection against accidentally overwriting the memory - there's some
very well hidden bug in Minic's RX logic which sometimes causes an overwrite of the memory outside
the buffer. */
lo = (uint32_t) minic.rx_base >> 2;
hi = ((uint32_t) minic.rx_base >> 2) + (sizeof(dma_rx_buf) >> 2) - 1;
minic_writel(MINIC_REG_MPROT,
MINIC_MPROT_LO_W(lo) | MINIC_MPROT_HI_W(hi));
minic.tx_base = dma_tx_buf;
minic.tx_size = MINIC_DMA_TX_BUF_SIZE >> 2;
minic.tx_count = 0;
minic.rx_count = 0;
minic_new_rx_buffer();
minic_writel(MINIC_REG_EIC_IER, MINIC_EIC_IER_RX);
}
......@@ -195,87 +100,69 @@ int minic_rx_frame(struct wr_ethhdr *hdr, uint8_t * payload, uint32_t buf_size,
if (!(minic_readl(MINIC_REG_EIC_ISR) & MINIC_EIC_ISR_RX))
return 0;
desc_hdr = *minic.rx_head;
if (!RX_DESC_VALID(desc_hdr)) { /* invalid descriptor? Weird, the RX_ADDR seems to be saying something different. Ignore the packet and purge the RX buffer. */
//invalid descriptor ? then probably the interrupt was generated by full rx buffer
if (minic_readl(MINIC_REG_MCR) & MINIC_MCR_RX_FULL) {
minic_new_rx_buffer();
} else {
//otherwise, weird !!
pp_printf("invalid descriptor @%x = %x\n",
(uint32_t) minic.rx_head, desc_hdr);
minic_new_rx_buffer();
//minic_new_rx_buffer();
}
return 0;
}
frame_size = RX_DESC_SIZE(desc_hdr);
num_words = ((frame_size + 3) >> 2) + 1;
/* valid packet */
if (!RX_DESC_ERROR(desc_hdr)) {
if (RX_DESC_HAS_OOB(desc_hdr) && hwts != NULL) {
uint32_t counter_r, counter_f, counter_ppsg;
uint64_t sec;
int cntr_diff;
uint16_t dhdr;
//if (RX_DESC_HAS_OOB(desc_hdr) && hwts != NULL) {
// uint32_t counter_r, counter_f, counter_ppsg;
// uint64_t sec;
// int cntr_diff;
// uint16_t dhdr;
frame_size -= RX_OOB_SIZE;
// frame_size -= RX_OOB_SIZE;
/* fixme: ugly way of doing unaligned read */
minic_rx_memcpy((uint8_t *) & raw_ts,
(uint8_t *) minic.rx_head
+ frame_size + 6, 4);
minic_rx_memcpy((uint8_t *) & dhdr,
(uint8_t *) minic.rx_head +
frame_size + 4, 2);
EXPLODE_WR_TIMESTAMP(raw_ts, counter_r, counter_f);
// /* fixme: ugly way of doing unaligned read */
// minic_rx_memcpy((uint8_t *) & raw_ts,
// (uint8_t *) minic.rx_head
// + frame_size + 6, 4);
// minic_rx_memcpy((uint8_t *) & dhdr,
// (uint8_t *) minic.rx_head +
// frame_size + 4, 2);
// EXPLODE_WR_TIMESTAMP(raw_ts, counter_r, counter_f);
shw_pps_gen_get_time(&sec, &counter_ppsg);
// shw_pps_gen_get_time(&sec, &counter_ppsg);
if (counter_r > 3 * REF_CLOCK_FREQ_HZ / 4
&& counter_ppsg < 250000000)
sec--;
// if (counter_r > 3 * REF_CLOCK_FREQ_HZ / 4
// && counter_ppsg < 250000000)
// sec--;
hwts->sec = sec & 0x7fffffff;
// hwts->sec = sec & 0x7fffffff;
cntr_diff = (counter_r & F_COUNTER_MASK) - counter_f;
// cntr_diff = (counter_r & F_COUNTER_MASK) - counter_f;
if (cntr_diff == 1 || cntr_diff == (-F_COUNTER_MASK))
hwts->ahead = 1;
else
hwts->ahead = 0;
// if (cntr_diff == 1 || cntr_diff == (-F_COUNTER_MASK))
// hwts->ahead = 1;
// else
// hwts->ahead = 0;
hwts->nsec = counter_r * (REF_CLOCK_PERIOD_PS / 1000);
hwts->valid = (dhdr & RXOOB_TS_INCORRECT) ? 0 : 1;
}
// hwts->nsec = counter_r * (REF_CLOCK_PERIOD_PS / 1000);
// hwts->valid = (dhdr & RXOOB_TS_INCORRECT) ? 0 : 1;
//}
payload_size = frame_size - ETH_HEADER_SIZE;
n_recvd = (buf_size < payload_size ? buf_size : payload_size);
minic.rx_count++;
minic_rx_memcpy((void *)hdr, (void *)minic.rx_head + 4,
ETH_HEADER_SIZE);
minic_rx_memcpy(payload, (void *)minic.rx_head + 4
+ ETH_HEADER_SIZE, n_recvd);
} else {
n_recvd = -1;
}
minic_rxbuf_free(num_words);
minic.rx_head = (uint32_t *)((uint32_t)minic.rx_base +
((uint32_t) minic.rx_head
+ (num_words << 2) - (uint32_t)minic.rx_base)
% (minic.rx_size << 2));
cur_avail = minic_readl(MINIC_REG_RX_AVAIL) & 0xFFFFFF; /* 24-bit field */
/*empty buffer->no more received packets, or packet reception in progress but not done */
if (!RX_DESC_VALID(*minic.rx_head)) {
//if (!RX_DESC_VALID(*minic.rx_head)) {
if (minic_readl(MINIC_REG_MCR) & MINIC_MCR_RX_FULL)
minic_new_rx_buffer();
//minic_new_rx_buffer();
minic_writel(MINIC_REG_EIC_ISR, MINIC_EIC_ISR_RX);
}
//}
return n_recvd;
}
......@@ -287,18 +174,11 @@ int minic_tx_frame(struct wr_ethhdr_vlan *hdr, uint8_t *payload, uint32_t size,
uint8_t ts_valid;
int i, hsize;
minic_new_tx_buffer();
if (hdr->ethtype == htons(0x8100))
hsize = sizeof(struct wr_ethhdr_vlan);
else
hsize = sizeof(struct wr_ethhdr);
memset((void *)minic.tx_head, 0x0, size + hsize + 4);
memcpy((void *)minic.tx_head + 4, hdr, hsize);
memcpy((void *)minic.tx_head + 4 + hsize, payload, size);
size += hsize;
if (size < 60)
size = 60;
......@@ -306,13 +186,13 @@ int minic_tx_frame(struct wr_ethhdr_vlan *hdr, uint8_t *payload, uint32_t size,
d_hdr = 0;
if (hwts)
d_hdr = TX_DESC_WITH_OOB | (WRPC_FID << 12);
//if (hwts)
// d_hdr = TX_DESC_WITH_OOB | (WRPC_FID << 12);
d_hdr |= TX_DESC_VALID | nwords;
//d_hdr |= TX_DESC_VALID | nwords;
*(volatile uint32_t *)(minic.tx_head) = d_hdr;
*(volatile uint32_t *)(minic.tx_head + nwords) = 0;
//*(volatile uint32_t *)(minic.tx_head) = d_hdr;
//*(volatile uint32_t *)(minic.tx_head + nwords) = 0;
mcr = minic_readl(MINIC_REG_MCR);
minic_writel(MINIC_REG_MCR, mcr | MINIC_MCR_TX_START);
......
include/hw/minic_regs.h
View file @ 5ccade7c
......@@ -3,7 +3,7 @@
* File : minic_regs.h
* Author : auto-generated by wbgen2 from mini_nic.wb
* Created : Thu Mar 7 14:45:52 2013
* Created : Thu Oct 27 16:54:11 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -42,11 +42,17 @@
/* definitions for field: TX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_TX_ERROR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: TX_FIFO_EMPTY in reg: miNIC Control Register */
#define MINIC_MCR_TX_EMPTY WBGEN2_GEN_MASK(3, 1)
/* definitions for field: TX_FIFO_FULL in reg: miNIC Control Register */
#define MINIC_MCR_TX_FULL WBGEN2_GEN_MASK(4, 1)
/* definitions for field: RX DMA ready in reg: miNIC Control Register */
#define MINIC_MCR_RX_READY WBGEN2_GEN_MASK(8, 1)
/* definitions for field: RX DMA buffer full in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL WBGEN2_GEN_MASK(9, 1)
/* definitions for field: RX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_RX_ERROR WBGEN2_GEN_MASK(9, 1)
/* definitions for field: RX DMA enable in reg: miNIC Control Register */
#define MINIC_MCR_RX_EN WBGEN2_GEN_MASK(10, 1)
......@@ -54,19 +60,57 @@
/* definitions for field: TX TS ready in reg: miNIC Control Register */
#define MINIC_MCR_TX_TS_READY WBGEN2_GEN_MASK(11, 1)
/* definitions for field: RX_FIFO_EMPTY in reg: miNIC Control Register */
#define MINIC_MCR_RX_EMPTY WBGEN2_GEN_MASK(12, 1)
/* definitions for field: RX_FIFO_FULL in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL WBGEN2_GEN_MASK(13, 1)
/* definitions for field: RX Accepted Packet Classes in reg: miNIC Control Register */
#define MINIC_MCR_RX_CLASS_MASK WBGEN2_GEN_MASK(16, 8)
#define MINIC_MCR_RX_CLASS_SHIFT 16
#define MINIC_MCR_RX_CLASS_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define MINIC_MCR_RX_CLASS_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for register: TX DMA Address */
/* definitions for field: Regs map version in reg: miNIC Control Register */
#define MINIC_MCR_VER_MASK WBGEN2_GEN_MASK(24, 4)
#define MINIC_MCR_VER_SHIFT 24
#define MINIC_MCR_VER_W(value) WBGEN2_GEN_WRITE(value, 24, 4)
#define MINIC_MCR_VER_R(reg) WBGEN2_GEN_READ(reg, 24, 4)
/* definitions for register: TX FIFO Register */
/* definitions for field: Data to send in reg: TX FIFO Register */
#define MINIC_TX_FIFO_DAT_MASK WBGEN2_GEN_MASK(0, 16)
#define MINIC_TX_FIFO_DAT_SHIFT 0
#define MINIC_TX_FIFO_DAT_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MINIC_TX_FIFO_DAT_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Data type in reg: TX FIFO Register */
#define MINIC_TX_FIFO_TYPE_MASK WBGEN2_GEN_MASK(16, 2)
#define MINIC_TX_FIFO_TYPE_SHIFT 16
#define MINIC_TX_FIFO_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 2)
#define MINIC_TX_FIFO_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 2)
/* definitions for register: RX FIFO Register */
/* definitions for field: Data to send in reg: RX FIFO Register */
#define MINIC_RX_FIFO_DAT_MASK WBGEN2_GEN_MASK(0, 16)
#define MINIC_RX_FIFO_DAT_SHIFT 0
#define MINIC_RX_FIFO_DAT_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MINIC_RX_FIFO_DAT_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: RX DMA Address */
/* definitions for field: Data type in reg: RX FIFO Register */
#define MINIC_RX_FIFO_TYPE_MASK WBGEN2_GEN_MASK(16, 2)
#define MINIC_RX_FIFO_TYPE_SHIFT 16
#define MINIC_RX_FIFO_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 2)
#define MINIC_RX_FIFO_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 2)
/* definitions for register: RX buffer size register */
/* definitions for field: RX_FIFO_EMPTY in reg: RX FIFO Register */
#define MINIC_RX_FIFO_EMPTY WBGEN2_GEN_MASK(30, 1)
/* definitions for register: RX buffer available words register */
/* definitions for field: RX_FIFO_FULL in reg: RX FIFO Register */
#define MINIC_RX_FIFO_FULL WBGEN2_GEN_MASK(31, 1)
/* definitions for register: TX timestamp register 0 */
......@@ -163,14 +207,14 @@
#define MINIC_EIC_ISR_TXTS WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG miNIC Control Register */
#define MINIC_REG_MCR 0x00000000
/* [0x4]: REG TX DMA Address */
#define MINIC_REG_TX_ADDR 0x00000004
/* [0x8]: REG RX DMA Address */
#define MINIC_REG_RX_ADDR 0x00000008
/* [0xc]: REG RX buffer size register */
#define MINIC_REG_RX_SIZE 0x0000000c
/* [0x10]: REG RX buffer available words register */
#define MINIC_REG_RX_AVAIL 0x00000010
/* [0x4]: REG TX FIFO Register */
#define MINIC_REG_TX_FIFO 0x00000004
/* [0x8]: REG RX FIFO Register */
#define MINIC_REG_RX_FIFO 0x00000008
/* [0xc]: REG reserved 1 */
#define MINIC_REG_RESV_1 0x0000000c
/* [0x10]: REG reserved 2 */
#define MINIC_REG_RESV_2 0x00000010
/* [0x14]: REG TX timestamp register 0 */
#define MINIC_REG_TSR0 0x00000014
/* [0x18]: REG TX timestamp register 1 */
......
include/minic.h
View file @ 5ccade7c
......@@ -34,11 +34,6 @@ struct wr_ethhdr_vlan {
};
struct wr_minic {
volatile uint32_t *rx_head, *rx_base;
uint32_t rx_avail, rx_size;
volatile uint32_t *tx_head, *tx_base;
uint32_t tx_avail, tx_size;
int tx_count, rx_count;
};
......
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