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Software for White Rabbit PTP Core
Commit 5a012c07 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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ertm14: hack for hardware dithered softpll + gain adjust for helper

parent 249b49fe
Pipeline #4725 passed with stage
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    boards/ertm14/board.c
    View file @ 5a012c07
    ......@@ -589,13 +589,13 @@ static void ertm14_spll_setup(void)
    gs->stages[0].kp = -4000 * 16;
    gs->stages[0].ki = -5 * 16;
    gs->stages[0].lock_samples = 30000;
    gs->stages[0].shift = 16;
    gs->stages[0].shift = 8;
    /* once it's locked, the loop bandwidth is switched to ~0.1 Hz to filter out WR link added phase noise */
    gs->stages[1].kp = -3000;
    gs->stages[1].ki = -5;
    gs->stages[1].lock_samples = 10000;
    gs->stages[1].shift = 16;
    gs->stages[1].shift = 8;
    // disable 2nd stage for DOT050 and Morion OCXO
    if ( board.mode & ERTM14_MODE_WITHOUT_ERTM15 )
    ......@@ -615,6 +615,7 @@ static void ertm14_spll_setup(void)
    #endif
    spll_set_gain_schedule( gs );
    spll_set_pi_gain( SPLL_LOOP_HELPER, 0, -700, -2 );
    // Aux clock 0 is used for 'factory' calibration of CLKAB/LO/REF outputs.
    spll_set_aux_mode( 0, SPLL_AUX_MODE_PHASE_MONITOR );
    ......
    include/hw/softpll_regs.h
    View file @ 5a012c07
    ......@@ -3,7 +3,7 @@
    * File : softpll_regs.h
    * Author : auto-generated by wbgen2 from spll_wb_slave.wb
    * Created : Thu Dec 3 15:09:41 2015
    * Created : Sun Jul 16 23:36:22 2023
    * Standard : ANSI C
    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
    ......@@ -14,7 +14,11 @@
    #ifndef __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
    #define __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
    #ifdef __KERNEL__
    #include <linux/types.h>
    #else
    #include <inttypes.h>
    #endif
    #if defined( __GNUC__)
    #define PACKED __attribute__ ((packed))
    ......@@ -89,27 +93,42 @@
    /* definitions for register: Aligner Counter IN register */
    /* definitions for register: DMTD VCO Frequency */
    /* definitions for register: DMTD stat control */
    /* definitions for field: SAMPLES in reg: DMTD stat control */
    #define SPLL_DMTD_STAT_CR_SAMPLES_MASK WBGEN2_GEN_MASK(0, 16)
    #define SPLL_DMTD_STAT_CR_SAMPLES_SHIFT 0
    #define SPLL_DMTD_STAT_CR_SAMPLES_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
    #define SPLL_DMTD_STAT_CR_SAMPLES_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
    /* definitions for field: VALID in reg: DMTD stat control */
    #define SPLL_DMTD_STAT_CR_VALID WBGEN2_GEN_MASK(16, 1)
    /* definitions for field: RST in reg: DMTD stat control */
    #define SPLL_DMTD_STAT_CR_RST WBGEN2_GEN_MASK(17, 1)
    /* definitions for field: FREQ in reg: DMTD VCO Frequency */
    #define SPLL_F_DMTD_FREQ_MASK WBGEN2_GEN_MASK(0, 28)
    #define SPLL_F_DMTD_FREQ_SHIFT 0
    #define SPLL_F_DMTD_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
    #define SPLL_F_DMTD_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
    /* definitions for field: MINMAX_SEL in reg: DMTD stat control */
    #define SPLL_DMTD_STAT_CR_MINMAX_SEL WBGEN2_GEN_MASK(18, 1)
    /* definitions for field: VALID in reg: DMTD VCO Frequency */
    #define SPLL_F_DMTD_VALID WBGEN2_GEN_MASK(28, 1)
    /* definitions for field: CHAN_SEL in reg: DMTD stat control */
    #define SPLL_DMTD_STAT_CR_CHAN_SEL_MASK WBGEN2_GEN_MASK(19, 4)
    #define SPLL_DMTD_STAT_CR_CHAN_SEL_SHIFT 19
    #define SPLL_DMTD_STAT_CR_CHAN_SEL_W(value) WBGEN2_GEN_WRITE(value, 19, 4)
    #define SPLL_DMTD_STAT_CR_CHAN_SEL_R(reg) WBGEN2_GEN_READ(reg, 19, 4)
    /* definitions for register: REF VCO Frequency */
    /* definitions for register: DMTD stat values */
    /* definitions for field: FREQ in reg: REF VCO Frequency */
    #define SPLL_F_REF_FREQ_MASK WBGEN2_GEN_MASK(0, 28)
    #define SPLL_F_REF_FREQ_SHIFT 0
    #define SPLL_F_REF_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
    #define SPLL_F_REF_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
    /* definitions for field: HIGH in reg: DMTD stat values */
    #define SPLL_DMTD_STAT_VAL_HIGH_MASK WBGEN2_GEN_MASK(0, 16)
    #define SPLL_DMTD_STAT_VAL_HIGH_SHIFT 0
    #define SPLL_DMTD_STAT_VAL_HIGH_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
    #define SPLL_DMTD_STAT_VAL_HIGH_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
    /* definitions for field: VALID in reg: REF VCO Frequency */
    #define SPLL_F_REF_VALID WBGEN2_GEN_MASK(28, 1)
    /* definitions for field: LOW in reg: DMTD stat values */
    #define SPLL_DMTD_STAT_VAL_LOW_MASK WBGEN2_GEN_MASK(16, 16)
    #define SPLL_DMTD_STAT_VAL_LOW_SHIFT 16
    #define SPLL_DMTD_STAT_VAL_LOW_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
    #define SPLL_DMTD_STAT_VAL_LOW_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
    /* definitions for register: EXT VCO Frequency */
    ......@@ -145,16 +164,16 @@
    /* definitions for register: Main DAC Output */
    /* definitions for field: DAC value in reg: Main DAC Output */
    #define SPLL_DAC_MAIN_VALUE_MASK WBGEN2_GEN_MASK(0, 16)
    #define SPLL_DAC_MAIN_VALUE_MASK WBGEN2_GEN_MASK(0, 24)
    #define SPLL_DAC_MAIN_VALUE_SHIFT 0
    #define SPLL_DAC_MAIN_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
    #define SPLL_DAC_MAIN_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
    #define SPLL_DAC_MAIN_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
    #define SPLL_DAC_MAIN_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
    /* definitions for field: DAC select in reg: Main DAC Output */
    #define SPLL_DAC_MAIN_DAC_SEL_MASK WBGEN2_GEN_MASK(16, 4)
    #define SPLL_DAC_MAIN_DAC_SEL_SHIFT 16
    #define SPLL_DAC_MAIN_DAC_SEL_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
    #define SPLL_DAC_MAIN_DAC_SEL_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
    #define SPLL_DAC_MAIN_DAC_SEL_MASK WBGEN2_GEN_MASK(24, 4)
    #define SPLL_DAC_MAIN_DAC_SEL_SHIFT 24
    #define SPLL_DAC_MAIN_DAC_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 4)
    #define SPLL_DAC_MAIN_DAC_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 4)
    /* definitions for register: DDMTD Deglitcher threshold */
    ......@@ -245,58 +264,58 @@
    #define SPLL_TRR_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
    PACKED struct SPLL_WB {
    /* [0x0]: REG SPLL Control/Status Register */
    uint32_t CSR;
    /* [0x4]: REG External Clock Control Register */
    uint32_t ECCR;
    /* [0x8]: REG Aligner Control Register */
    uint32_t AL_CR;
    /* [0xc]: REG Aligner Counter REF register */
    uint32_t AL_CREF;
    /* [0x10]: REG Aligner Counter IN register */
    uint32_t AL_CIN;
    /* [0x14]: REG DMTD VCO Frequency */
    uint32_t F_DMTD;
    /* [0x18]: REG REF VCO Frequency */
    uint32_t F_REF;
    /* [0x1c]: REG EXT VCO Frequency */
    uint32_t F_EXT;
    /* [0x20]: REG Output Channel Control Register */
    uint32_t OCCR;
    /* [0x24]: REG Reference Channel Tagging Enable Register */
    uint32_t RCER;
    /* [0x28]: REG Output Channel Tagging Enable Register */
    uint32_t OCER;
    /* padding to: 16 words */
    uint32_t __padding_0[5];
    /* [0x40]: REG Helper DAC Output */
    uint32_t DAC_HPLL;
    /* [0x44]: REG Main DAC Output */
    uint32_t DAC_MAIN;
    /* [0x48]: REG DDMTD Deglitcher threshold */
    uint32_t DEGLITCH_THR;
    /* [0x4c]: REG Debug FIFO Register - SPLL side */
    uint32_t DFR_SPLL;
    /* padding to: 24 words */
    uint32_t __padding_1[4];
    /* [0x60]: REG Interrupt disable register */
    uint32_t EIC_IDR;
    /* [0x64]: REG Interrupt enable register */
    uint32_t EIC_IER;
    /* [0x68]: REG Interrupt mask register */
    uint32_t EIC_IMR;
    /* [0x6c]: REG Interrupt status register */
    uint32_t EIC_ISR;
    /* [0x70]: REG FIFO 'Debug FIFO Register - Host side' data output register 0 */
    uint32_t DFR_HOST_R0;
    /* [0x74]: REG FIFO 'Debug FIFO Register - Host side' data output register 1 */
    uint32_t DFR_HOST_R1;
    /* [0x78]: REG FIFO 'Debug FIFO Register - Host side' control/status register */
    uint32_t DFR_HOST_CSR;
    /* [0x7c]: REG FIFO 'Tag Readout Register' data output register 0 */
    uint32_t TRR_R0;
    /* [0x80]: REG FIFO 'Tag Readout Register' control/status register */
    uint32_t TRR_CSR;
    /* [0x0]: REG SPLL Control/Status Register */
    uint32_t CSR;
    /* [0x4]: REG External Clock Control Register */
    uint32_t ECCR;
    /* [0x8]: REG Aligner Control Register */
    uint32_t AL_CR;
    /* [0xc]: REG Aligner Counter REF register */
    uint32_t AL_CREF;
    /* [0x10]: REG Aligner Counter IN register */
    uint32_t AL_CIN;
    /* [0x14]: REG DMTD stat control */
    uint32_t DMTD_STAT_CR;
    /* [0x18]: REG DMTD stat values */
    uint32_t DMTD_STAT_VAL;
    /* [0x1c]: REG EXT VCO Frequency */
    uint32_t F_EXT;
    /* [0x20]: REG Output Channel Control Register */
    uint32_t OCCR;
    /* [0x24]: REG Reference Channel Tagging Enable Register */
    uint32_t RCER;
    /* [0x28]: REG Output Channel Tagging Enable Register */
    uint32_t OCER;
    /* padding to: 16 words */
    uint32_t __padding_0[5];
    /* [0x40]: REG Helper DAC Output */
    uint32_t DAC_HPLL;
    /* [0x44]: REG Main DAC Output */
    uint32_t DAC_MAIN;
    /* [0x48]: REG DDMTD Deglitcher threshold */
    uint32_t DEGLITCH_THR;
    /* [0x4c]: REG Debug FIFO Register - SPLL side */
    uint32_t DFR_SPLL;
    /* padding to: 24 words */
    uint32_t __padding_1[4];
    /* [0x60]: REG Interrupt disable register */
    uint32_t EIC_IDR;
    /* [0x64]: REG Interrupt enable register */
    uint32_t EIC_IER;
    /* [0x68]: REG Interrupt mask register */
    uint32_t EIC_IMR;
    /* [0x6c]: REG Interrupt status register */
    uint32_t EIC_ISR;
    /* [0x70]: REG FIFO 'Debug FIFO Register - Host side' data output register 0 */
    uint32_t DFR_HOST_R0;
    /* [0x74]: REG FIFO 'Debug FIFO Register - Host side' data output register 1 */
    uint32_t DFR_HOST_R1;
    /* [0x78]: REG FIFO 'Debug FIFO Register - Host side' control/status register */
    uint32_t DFR_HOST_CSR;
    /* [0x7c]: REG FIFO 'Tag Readout Register' data output register 0 */
    uint32_t TRR_R0;
    /* [0x80]: REG FIFO 'Tag Readout Register' control/status register */
    uint32_t TRR_CSR;
    };
    #endif
    ppsi @ 61f7d34d
    Subproject commit 168f5e44aa3028bbbcd41211e724a0e7ae2b5783
    Subproject commit 61f7d34d92e473baee52cfc89e14910226940bf1
    softpll/softpll_ng.c
    View file @ 5a012c07
    ......@@ -845,24 +845,7 @@ void spll_set_dac(int index, int value)
    int spll_measure_frequency(int osc)
    {
    volatile uint32_t *reg;
    switch(osc) {
    case SPLL_OSC_REF:
    reg = &SPLL->F_REF;
    break;
    case SPLL_OSC_DMTD:
    reg = &SPLL->F_DMTD;
    break;
    case SPLL_OSC_EXT:
    reg = &SPLL->F_EXT;
    break;
    default:
    return 0;
    }
    timer_delay_ms(2000);
    return (*reg ) & (0xfffffff);
    return 0;
    }
    void spll_set_gain_schedule( spll_gain_schedule_t* sch )
    ......
    softpll/spll_common.c
    View file @ 5a012c07
    ......@@ -14,6 +14,7 @@
    #include <wrc.h>
    #include "softpll_ng.h"
    #if 0
    static int gen_dither_lfsr( int pi_shift )
    {
    static uint16_t lfsr = 0xACE1u;
    ......@@ -30,6 +31,8 @@ static int gen_dither_lfsr( int pi_shift )
    return d;
    }
    #endif
    int pi_update(spll_pi_t *pi, int x)
    {
    int64_t i_new;
    ......@@ -39,7 +42,7 @@ int pi_update(spll_pi_t *pi, int x)
    int64_t y_preround = (i_new + (int64_t) x * pi->kp) + ( 1 << (pi->shift - 1) );
    int dither = pi->dithered ? gen_dither_lfsr( pi->shift - 1 ) : 0;
    int dither = 0; //pi->dithered ? gen_dither_lfsr( pi->shift - 1 ) : 0;
    y = ( (y_preround + dither) >> pi->shift) + pi->bias;
    /* clamping (output has to be in <y_min, y_max>) and
    ......
    softpll/spll_helper.c
    View file @ 5a012c07
    ......@@ -14,8 +14,8 @@
    void helper_very_init( struct spll_helper_state *s )
    {
    /* Phase branch PI controller */
    s->pi.y_min = 5;
    s->pi.y_max = (1 << DAC_BITS) - 5;
    s->pi.y_min = 5 + 256;
    s->pi.y_max = (1 << (DAC_BITS+8)) - 5 - 256;
    #if defined(CONFIG_WR_NODE)
    s->pi.kp = -150;//(int)(0.3 * 32.0 * 16.0); // / 2;
    s->pi.ki = -2;//(int)(0.03 * 32.0 * 3.0); // / 2;
    ......@@ -24,7 +24,7 @@ void helper_very_init( struct spll_helper_state *s )
    s->pi.ki = 2;
    #endif
    s->pi.anti_windup = 1;
    s->pi.shift = PI_FRACBITS;
    s->pi.shift = PI_FRACBITS - 8;
    /* Phase branch lock detection */
    s->ld.threshold = 200;
    ......
    softpll/spll_main.c
    View file @ 5a012c07
    ......@@ -28,11 +28,11 @@ void mpll_init(struct spll_main_state *s, int id_ref, int id_out)
    s->ps_freeze = 0;
    s->vco_freeze = 0;
    s->pi.y_min = 5;
    s->pi.y_max = 65530;
    s->pi.y_min = 5 << 8;
    s->pi.y_max = 65530 << 8;
    s->pi.anti_windup = 1;
    s->pi.bias = 30000;
    s->pi.shift = PI_FRACBITS;
    s->pi.bias = 30000 << 8;
    s->pi.shift = PI_FRACBITS - 8;
    #if defined(CONFIG_TARGET_WR_SWITCH)
    if (spll_ljd_present) {
    s->pi.kp = 2000;
    ......
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