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Software for White Rabbit PTP Core
Commit 59e6659c authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Adam Wujek
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[wbgen-ver] updated streamers and diags to have version of the wbgen registers

parent 4f95bf99
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include/hw/wr_streamers.h
View file @ 59e6659c
...@@ -3,7 +3,8 @@ ...@@ -3,7 +3,8 @@
* File : ./doc/wr_streamers.h * File : ./doc/wr_streamers.h
* Author : auto-generated by wbgen2 from wr_streamers_wb.wb * Author : auto-generated by wbgen2 from wr_streamers_wb.wb
* Created : Wed May 17 08:49:53 2017 * Created : Tue Jun 20 08:53:54 2017
* Version : 0x00000001
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_streamers_wb.wb
...@@ -34,6 +35,17 @@ ...@@ -34,6 +35,17 @@
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value)) #define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif #endif
/* version definition */
#define WBGEN2_WR_STREAMERS_VERSION 0x00000001
/* definitions for register: Version register */
/* definitions for field: Version identifier in reg: Version register */
#define WR_STREAMERS_VER_ID_MASK WBGEN2_GEN_MASK(0, 32)
#define WR_STREAMERS_VER_ID_SHIFT 0
#define WR_STREAMERS_VER_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WR_STREAMERS_VER_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Statistics status and ctrl register */ /* definitions for register: Statistics status and ctrl register */
...@@ -348,71 +360,73 @@ ...@@ -348,71 +360,73 @@
#define WR_STREAMERS_DUMMY_DUMMY_R(reg) WBGEN2_GEN_READ(reg, 0, 32) #define WR_STREAMERS_DUMMY_DUMMY_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
PACKED struct WR_STREAMERS_WB { PACKED struct WR_STREAMERS_WB {
/* [0x0]: REG Statistics status and ctrl register */ /* [0x0]: REG Version register */
uint32_t SSCR1; uint32_t VER;
/* [0x4]: REG Statistics status and ctrl register */ /* [0x4]: REG Statistics status and ctrl register */
uint32_t SSCR2; uint32_t SSCR1;
/* [0x8]: REG Statistics status and ctrl register */ /* [0x8]: REG Statistics status and ctrl register */
uint32_t SSCR2;
/* [0xc]: REG Statistics status and ctrl register */
uint32_t SSCR3; uint32_t SSCR3;
/* [0xc]: REG Rx statistics */
uint32_t RX_STAT0;
/* [0x10]: REG Rx statistics */ /* [0x10]: REG Rx statistics */
uint32_t RX_STAT0;
/* [0x14]: REG Rx statistics */
uint32_t RX_STAT1; uint32_t RX_STAT1;
/* [0x14]: REG Tx statistics */
uint32_t TX_STAT2;
/* [0x18]: REG Tx statistics */ /* [0x18]: REG Tx statistics */
uint32_t TX_STAT2;
/* [0x1c]: REG Tx statistics */
uint32_t TX_STAT3; uint32_t TX_STAT3;
/* [0x1c]: REG Rx statistics */
uint32_t RX_STAT4;
/* [0x20]: REG Rx statistics */ /* [0x20]: REG Rx statistics */
uint32_t RX_STAT5; uint32_t RX_STAT4;
/* [0x24]: REG Rx statistics */ /* [0x24]: REG Rx statistics */
uint32_t RX_STAT6; uint32_t RX_STAT5;
/* [0x28]: REG Rx statistics */ /* [0x28]: REG Rx statistics */
uint32_t RX_STAT7; uint32_t RX_STAT6;
/* [0x2c]: REG Rx statistics */ /* [0x2c]: REG Rx statistics */
uint32_t RX_STAT8; uint32_t RX_STAT7;
/* [0x30]: REG Rx statistics */ /* [0x30]: REG Rx statistics */
uint32_t RX_STAT9; uint32_t RX_STAT8;
/* [0x34]: REG Rx statistics */ /* [0x34]: REG Rx statistics */
uint32_t RX_STAT10; uint32_t RX_STAT9;
/* [0x38]: REG Rx statistics */ /* [0x38]: REG Rx statistics */
uint32_t RX_STAT11; uint32_t RX_STAT10;
/* [0x3c]: REG Rx statistics */ /* [0x3c]: REG Rx statistics */
uint32_t RX_STAT12; uint32_t RX_STAT11;
/* [0x40]: REG Rx statistics */ /* [0x40]: REG Rx statistics */
uint32_t RX_STAT12;
/* [0x44]: REG Rx statistics */
uint32_t RX_STAT13; uint32_t RX_STAT13;
/* [0x44]: REG Tx Config Reg 0 */ /* [0x48]: REG Tx Config Reg 0 */
uint32_t TX_CFG0; uint32_t TX_CFG0;
/* [0x48]: REG Tx Config Reg 1 */ /* [0x4c]: REG Tx Config Reg 1 */
uint32_t TX_CFG1; uint32_t TX_CFG1;
/* [0x4c]: REG Tx Config Reg 2 */ /* [0x50]: REG Tx Config Reg 2 */
uint32_t TX_CFG2; uint32_t TX_CFG2;
/* [0x50]: REG Tx Config Reg 3 */ /* [0x54]: REG Tx Config Reg 3 */
uint32_t TX_CFG3; uint32_t TX_CFG3;
/* [0x54]: REG Tx Config Reg 4 */
uint32_t TX_CFG4;
/* [0x58]: REG Tx Config Reg 4 */ /* [0x58]: REG Tx Config Reg 4 */
uint32_t TX_CFG4;
/* [0x5c]: REG Tx Config Reg 4 */
uint32_t TX_CFG5; uint32_t TX_CFG5;
/* [0x5c]: REG Rx Config Reg 0 */ /* [0x60]: REG Rx Config Reg 0 */
uint32_t RX_CFG0; uint32_t RX_CFG0;
/* [0x60]: REG Rx Config Reg 1 */ /* [0x64]: REG Rx Config Reg 1 */
uint32_t RX_CFG1; uint32_t RX_CFG1;
/* [0x64]: REG Rx Config Reg 2 */ /* [0x68]: REG Rx Config Reg 2 */
uint32_t RX_CFG2; uint32_t RX_CFG2;
/* [0x68]: REG Rx Config Reg 3 */ /* [0x6c]: REG Rx Config Reg 3 */
uint32_t RX_CFG3; uint32_t RX_CFG3;
/* [0x6c]: REG Rx Config Reg 4 */ /* [0x70]: REG Rx Config Reg 4 */
uint32_t RX_CFG4; uint32_t RX_CFG4;
/* [0x70]: REG Rx Config Reg 5 */ /* [0x74]: REG Rx Config Reg 5 */
uint32_t RX_CFG5; uint32_t RX_CFG5;
/* [0x74]: REG TxRx Config Override */ /* [0x78]: REG TxRx Config Override */
uint32_t CFG; uint32_t CFG;
/* [0x78]: REG DBG Control register */ /* [0x7c]: REG DBG Control register */
uint32_t DBG_CTRL; uint32_t DBG_CTRL;
/* [0x7c]: REG DBG Data */ /* [0x80]: REG DBG Data */
uint32_t DBG_DATA; uint32_t DBG_DATA;
/* [0x80]: REG Test value */ /* [0x84]: REG Test value */
uint32_t DUMMY; uint32_t DUMMY;
}; };
......
include/hw/wrc_diags_regs.h
View file @ 59e6659c
...@@ -3,7 +3,8 @@ ...@@ -3,7 +3,8 @@
* File : wrc_diags_regs.h * File : wrc_diags_regs.h
* Author : auto-generated by wbgen2 from wrc_diags_wb.wb * Author : auto-generated by wbgen2 from wrc_diags_wb.wb
* Created : Mon May 8 13:58:25 2017 * Created : Tue Jun 20 09:59:03 2017
* Version : 0x00000001
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_diags_wb.wb
...@@ -34,6 +35,17 @@ ...@@ -34,6 +35,17 @@
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value)) #define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif #endif
/* version definition */
#define WBGEN2_WRC_DIAGS_VERSION 0x00000001
/* definitions for register: Version register */
/* definitions for field: Version identifier in reg: Version register */
#define WRC_DIAGS_VER_ID_MASK WBGEN2_GEN_MASK(0, 32)
#define WRC_DIAGS_VER_ID_SHIFT 0
#define WRC_DIAGS_VER_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WRC_DIAGS_VER_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Ctrl */ /* definitions for register: Ctrl */
...@@ -107,43 +119,45 @@ ...@@ -107,43 +119,45 @@
/* definitions for register: WRPC Diag: Board temperature [C degree] */ /* definitions for register: WRPC Diag: Board temperature [C degree] */
PACKED struct WRC_DIAGS_WB { PACKED struct WRC_DIAGS_WB {
/* [0x0]: REG Ctrl */ /* [0x0]: REG Version register */
uint32_t VER;
/* [0x4]: REG Ctrl */
uint32_t CTRL; uint32_t CTRL;
/* [0x4]: REG WRPC Diag: servo status */ /* [0x8]: REG WRPC Diag: servo status */
uint32_t WDIAG_SSTAT; uint32_t WDIAG_SSTAT;
/* [0x8]: REG WRPC Diag: Port status */ /* [0xc]: REG WRPC Diag: Port status */
uint32_t WDIAG_PSTAT; uint32_t WDIAG_PSTAT;
/* [0xc]: REG WRPC Diag: PTP state */ /* [0x10]: REG WRPC Diag: PTP state */
uint32_t WDIAG_PTPSTAT; uint32_t WDIAG_PTPSTAT;
/* [0x10]: REG WRPC Diag: AUX state */ /* [0x14]: REG WRPC Diag: AUX state */
uint32_t WDIAG_ASTAT; uint32_t WDIAG_ASTAT;
/* [0x14]: REG WRPC Diag: Tx PTP Frame cnts */ /* [0x18]: REG WRPC Diag: Tx PTP Frame cnts */
uint32_t WDIAG_TXFCNT; uint32_t WDIAG_TXFCNT;
/* [0x18]: REG WRPC Diag: Rx PTP Frame cnts */ /* [0x1c]: REG WRPC Diag: Rx PTP Frame cnts */
uint32_t WDIAG_RXFCNT; uint32_t WDIAG_RXFCNT;
/* [0x1c]: REG WRPC Diag:local time [msb of s] */ /* [0x20]: REG WRPC Diag:local time [msb of s] */
uint32_t WDIAG_SEC_MSB; uint32_t WDIAG_SEC_MSB;
/* [0x20]: REG WRPC Diag: local time [lsb of s] */ /* [0x24]: REG WRPC Diag: local time [lsb of s] */
uint32_t WDIAG_SEC_LSB; uint32_t WDIAG_SEC_LSB;
/* [0x24]: REG WRPC Diag: local time [ns] */ /* [0x28]: REG WRPC Diag: local time [ns] */
uint32_t WDIAG_NS; uint32_t WDIAG_NS;
/* [0x28]: REG WRPC Diag: Round trip (mu) [msb of ps] */ /* [0x2c]: REG WRPC Diag: Round trip (mu) [msb of ps] */
uint32_t WDIAG_MU_MSB; uint32_t WDIAG_MU_MSB;
/* [0x2c]: REG WRPC Diag: Round trip (mu) [lsb of ps] */ /* [0x30]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
uint32_t WDIAG_MU_LSB; uint32_t WDIAG_MU_LSB;
/* [0x30]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */ /* [0x34]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
uint32_t WDIAG_DMS_MSB; uint32_t WDIAG_DMS_MSB;
/* [0x34]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */ /* [0x38]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
uint32_t WDIAG_DMS_LSB; uint32_t WDIAG_DMS_LSB;
/* [0x38]: REG WRPC Diag: Total link asymmetry [ps] */ /* [0x3c]: REG WRPC Diag: Total link asymmetry [ps] */
uint32_t WDIAG_ASYM; uint32_t WDIAG_ASYM;
/* [0x3c]: REG WRPC Diag: Clock offset (cko) [ps] */ /* [0x40]: REG WRPC Diag: Clock offset (cko) [ps] */
uint32_t WDIAG_CKO; uint32_t WDIAG_CKO;
/* [0x40]: REG WRPC Diag: Phase setpoint (setp) [ps] */ /* [0x44]: REG WRPC Diag: Phase setpoint (setp) [ps] */
uint32_t WDIAG_SETP; uint32_t WDIAG_SETP;
/* [0x44]: REG WRPC Diag: Update counter (ucnt) */ /* [0x48]: REG WRPC Diag: Update counter (ucnt) */
uint32_t WDIAG_UCNT; uint32_t WDIAG_UCNT;
/* [0x48]: REG WRPC Diag: Board temperature [C degree] */ /* [0x4c]: REG WRPC Diag: Board temperature [C degree] */
uint32_t WDIAG_TEMP; uint32_t WDIAG_TEMP;
}; };
......
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