first attempt to mount eeprom storage

4e6377ed · Peter Jansweijer · 16c1b864 · 4e6377ed · 4e6377ed · 4e6377ed
Commit 4e6377ed authored Jul 08, 2020 by Peter Jansweijer
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Showing with 59 additions and 13 deletions

board.c boards/spec7/board.c +29 -13

board.h boards/spec7/board.h +1 -0

storage.c dev/storage.c +27 -0

storage.h include/storage.h +2 -0

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--- a/boards/spec7/board.c
+++ b/boards/spec7/board.c
 #include "board.h"
 #include "dev/bb_spi.h"
 #include "dev/spi_flash.h"
+#include "dev/bb_i2c.h"
+#include "dev/i2c_eeprom.h"
 #include "dev/syscon.h"
 #include "storage.h"

@@ -17,6 +19,8 @@ static struct gpio_pin pin_pll_sync_o        = { &board.gpio_aux, 7 };
 static struct gpio_pin pin_pll_wr_mode0_o    = { &board.gpio_aux, 8 };
 static struct gpio_pin pin_pll_wr_mode1_o    = { &board.gpio_aux, 9 };
 static struct gpio_pin pin_pll_clk_sel       = { &board.gpio_aux, 10 };
+static struct gpio_pin pin_eeprom_scl        = { &board.gpio_aux, 11 };
+static struct gpio_pin pin_eeprom_sda        = { &board.gpio_aux, 12 };

 static struct ltc6950_config ltc6950_base_config =
 #include "configs/ltc6950_base_config.h" 
@@ -33,7 +37,7 @@ void spec7_set_pll_wr_mode(int pll_wr_mode)
    gen_gpio_out( &pin_pll_wr_mode1_o, (pll_wr_mode & 0x2) ? 1 : 0);
 }

-void spec7_init()
+int spec7_init()
 {
    // Use free running dmtd clock for bootstrapping
    gen_gpio_out( &pin_pll_clk_sel, 0);
@@ -84,37 +88,49 @@ int wrc_board_early_init()

 int wrc_board_init()
 {
-    int memtype;
-    uint32_t sdbfs_entry;
-    uint32_t sector_size;
+    // int memtype;
+    // uint32_t sdbfs_entry;
+    // uint32_t sector_size;
+    struct i2c_bus            bus_i2c_eeprom;
+    struct i2c_eeprom_device  dev_i2c_eeprom;

    /*
     * declare GPIO pins and configure their directions for bit-banging SPI
     * limit SPI speed to 10MHz by setting bit_delay = CPU_CLOCK / 10^6
     */
-    bb_spi_create( &spi_wrc_flash,
-        &pin_sysc_spi_ncs,
-        &pin_sysc_spi_mosi,
-        &pin_sysc_spi_miso,
-        &pin_sysc_spi_sclk, CPU_CLOCK / 10000000 );
+    //bb_spi_create( &spi_wrc_flash,
+    //    &pin_sysc_spi_ncs,
+    //    &pin_sysc_spi_mosi,
+    //    &pin_sysc_spi_miso,
+    //    &pin_sysc_spi_sclk, CPU_CLOCK / 10000000 );
        
-    spi_wrc_flash.rd_falling_edge = 1;
+    //spi_wrc_flash.rd_falling_edge = 1;
+
+    /* create and initialize eeprom I2C bus */
+    bb_i2c_create(&bus_i2c_eeprom,
+         &pin_eeprom_scl,
+         &pin_eeprom_sda );
+    bb_i2c_init(&bus_i2c_eeprom);
+
+    i2c_eeprom_create(&dev_i2c_eeprom, &bus_i2c_eeprom, 0x50, 0x00);
+
+    storage_i2c_eeprom_create( &wrc_storage_dev, &dev_i2c_eeprom );

    /*
     * Read from gateware info about used memory. Currently only base
     * address and sector size for memtype flash is supported.
     */
-    get_storage_info(&memtype, &sdbfs_entry, &sector_size);
+    // get_storage_info(&memtype, &sdbfs_entry, &sector_size);

    /*
     * Initialize SPI flash and read its ID
     */
-    spi_flash_create( &wrc_flash_dev, &spi_wrc_flash, sector_size, sdbfs_entry);
+    // spi_flash_create( &wrc_flash_dev, &spi_wrc_flash, sector_size, sdbfs_entry);

    /*
     * Initialize storage subsystem with newly created SPI Flash
     */
-    storage_spiflash_create( &wrc_storage_dev, &wrc_flash_dev );
+    // storage_spiflash_create( &wrc_storage_dev, &wrc_flash_dev );

    /*
     * Mount SDBFS filesystem from storage.

--- a/boards/spec7/board.h
+++ b/boards/spec7/board.h
@@ -92,6 +92,7 @@
 #  define PLL_WR_MODE_GM 3
 
 void spec7_set_pll_wr_mode(int pll_wr_mode);
+int  spec7_init(void);

 struct spec7_board
 {

--- a/dev/storage.c
+++ b/dev/storage.c
@@ -68,6 +68,12 @@ struct storage_i2c_eeprom_priv
 	struct i2c_eeprom_device *dev;
 };

+/* Functions for I2C EEPROM access */
+const struct storage_rwops i2c_eeprom_rwops = {
+	i2c_eeprom_read,
+	i2c_eeprom_write,
+	i2c_eeprom_erase
+};

 /* Functions for Flash access */
 static int sdb_flash_read(struct storage_device *dev, int offset, void *buf, int count)
@@ -105,6 +111,14 @@ const int32_t spi_flash_default_entry_points[] =
 				0x600000,	/* after SVEC AFPGA bitstream */
 				-1 };

+const int32_t i2c_eeprom_default_entry_points[] = 
+{
+				0x000000,	/* eeprom base */
+				0x100,		/* second page in eeprom */
+				0x200,		/* IPMI with MultiRecord */
+				0x300,		/* IPMI with larger MultiRecord */
+				-1 };
+
 /* Functions for FRAM access */
 static int sdb_fram_read(struct storage_device *dev, int offset, void *buf, int count)
 {
@@ -190,6 +204,19 @@ void storage_spiflash_create(struct storage_device *dev, struct spi_flash_device
 	dev->flags = STORAGE_FLAG_DEVICE_OK;
 }

+void storage_i2c_eeprom_create(struct storage_device *dev, struct i2c_eeprom_device *eeprom)
+{
+	static const char* i2c_eeprom_str = "eeprom";
+	dev->name = (char *) i2c_eeprom_str;
+	dev->priv = eeprom;
+	dev->rwops = &i2c_eeprom_rwops;
+	dev->size = 8192;
+	dev->cfg_entry = 0;
+	dev->block_size = 1;
+	dev->entry_points = i2c_eeprom_default_entry_points;
+	dev->flags = STORAGE_FLAG_DEVICE_OK;
+}
+

 #if 0
 /*

--- a/include/storage.h
+++ b/include/storage.h
@@ -10,6 +10,7 @@
 #define __STORAGE_H

 #include "sfp.h"
+#include "dev/i2c_eeprom.h"

 // calibration parameter definitions. Board-specific.
 #define CAL_MAX_PARAMS 8
@@ -115,6 +116,7 @@ struct storage_device
 extern struct storage_device wrc_storage_dev;

 void storage_spiflash_create(struct storage_device *dev, struct spi_flash_device *flash);
+void storage_i2c_eeprom_create(struct storage_device *dev, struct i2c_eeprom_device *eeprom);

 void storage_init( struct i2c_bus *bus, int i2c_addr);