Commit 4802fef0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

phy_calibration: use target phase of 8ns to stay away from setup/hold time violation on TX datapath

parent 9995ef88
......@@ -40,8 +40,9 @@
#include "dev/clock_monitor.h"
#define LPDC_COARSE_PHASE_MIN_PS 15000 /* ps */
#define LPDC_COARSE_PHASE_MAX_PS 15500 /* ps */
/* middle of clock cycle seems the safest, we observed glitches around 15000->1000 ps */
#define LPDC_COARSE_PHASE_MIN_PS 8500 /* ps */
#define LPDC_COARSE_PHASE_MAX_PS 9000 /* ps */
#define LPDC_FINE_PHASE_TOLLERANCE_PS 40 /* ps */
......
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