Commit 44dd766e authored by Guido Visser's avatar Guido Visser

Set fraq bit to 16 bit in stead of 20

parent 7c23602e
Pipeline #421 failed with stages
in 10 seconds
......@@ -49,7 +49,7 @@ void mpll_init(struct spll_main_state *s, int id_ref,
// s->pi.ki = -10; // / 2;
s->pi.kp = -4000 * 16;; // / 2;
s->pi.ki = -5 * 16;; // / 2;
s->pi.shift = 20;
s->pi.shift = 16;
#else
#error "Please set CONFIG for wr switch or wr node"
#endif
......
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