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Software for White Rabbit PTP Core
Commit 3168c53e authored by broquet's avatar broquet
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i2c: add some code to adapt to fmc i2c mux on top

parent ac996c2a
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Showing with 79 additions and 14 deletions
dev/eeprom.c
View file @ 3168c53e
......@@ -57,6 +57,10 @@
* ------------------------------------------------
*/
//default time out in us to wait for i2c bus unlock
//~3s
#define BUS_TIME_OUT 3000000
uint8_t has_eeprom = 0;
static int i2cif, i2c_addr; /* globals, using the names we always used */
......@@ -67,10 +71,16 @@ void storage_init(int chosen_i2cif, int chosen_i2c_addr)
i2cif = chosen_i2cif;
i2c_addr = chosen_i2c_addr;
has_eeprom = 1;
if (!mi2c_devprobe(i2cif, i2c_addr))
if (!mi2c_devprobe(i2cif, i2c_addr))
has_eeprom = 0;
if(mi2c_poll(BUS_TIME_OUT))
{
has_eeprom = 1;
mi2c_lock();
if (!mi2c_devprobe(i2cif, i2c_addr))
if (!mi2c_devprobe(i2cif, i2c_addr))
has_eeprom = 0;
mi2c_unlock();
return;
}
return;
}
......@@ -84,6 +94,10 @@ static int eeprom_read(uint8_t i2cif, uint8_t i2c_addr, uint32_t offset,
if (!has_eeprom)
return -1;
if(!mi2c_poll(BUS_TIME_OUT))
return -2;
mi2c_lock();
mi2c_start(i2cif);
if (mi2c_put_byte(i2cif, i2c_addr << 1) < 0) {
mi2c_stop(i2cif);
......@@ -100,6 +114,7 @@ static int eeprom_read(uint8_t i2cif, uint8_t i2c_addr, uint32_t offset,
mi2c_get_byte(i2cif, &c, 1);
*buf++ = c;
mi2c_stop(i2cif);
mi2c_unlock();
return size;
}
......@@ -112,6 +127,10 @@ static int eeprom_write(uint8_t i2cif, uint8_t i2c_addr, uint32_t offset,
if (!has_eeprom)
return -1;
if(!mi2c_poll(BUS_TIME_OUT))
return -2;
mi2c_lock();
for (i = 0; i < size; i++) {
mi2c_start(i2cif);
......@@ -132,6 +151,7 @@ static int eeprom_write(uint8_t i2cif, uint8_t i2c_addr, uint32_t offset,
} while (busy);
}
mi2c_unlock();
return size;
}
......
dev/i2c.c
View file @ 3168c53e
......@@ -25,6 +25,37 @@ void mi2c_delay(void)
#define M_SCL_OUT(i, x) { gpio_out(i2c_if[i].scl, x); mi2c_delay(); }
#define M_SDA_IN(i) gpio_in(i2c_if[i].sda)
uint8_t mi2c_poll(uint32_t time_out_us)
{
//mi2c_delay ~= 5us if CPU frequency is 62.5MHz
uint32_t us = (uint32_t)(time_out_us / 5);
uint32_t i;
for(i = 0; i < us; i++)
{
//if FMC I2C bus is locked
if(gpio_in(WRC_FMC_I2C_LCK))
{
mi2c_delay();
}
else
{
return 1;
}
}
return 0;
}
void mi2c_lock(void)
{
gpio_out(WRC_FMC_I2C_SEL,1);
}
void mi2c_unlock(void)
{
gpio_out(WRC_FMC_I2C_SEL,0);
}
void mi2c_start(uint8_t i2cif)
{
M_SDA_OUT(i2cif, 0);
......
include/hw/wrc_syscon_regs.h
View file @ 3168c53e
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Wed Sep 25 14:35:39 2013
* Created : Mon Jun 6 15:29:37 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -86,6 +86,12 @@
/* definitions for field: SPI bitbanged MISO in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_SPI_MISO WBGEN2_GEN_MASK(13, 1)
/* definitions for field: Select FMC I2C bus in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_FMC_SEL WBGEN2_GEN_MASK(14, 1)
/* definitions for field: FMC I2C bus locked in reg: GPIO Set/Readback Register */
#define SYSC_GPSR_FMC_LCK WBGEN2_GEN_MASK(15, 1)
/* definitions for register: GPIO Clear Register */
/* definitions for field: Status LED in reg: GPIO Clear Register */
......@@ -115,6 +121,9 @@
/* definitions for field: SPI bitbanged MOSI in reg: GPIO Clear Register */
#define SYSC_GPCR_SPI_MOSI WBGEN2_GEN_MASK(12, 1)
/* definitions for field: Select FMC I2C bus in reg: GPIO Clear Register */
#define SYSC_GPCR_FMC_SEL WBGEN2_GEN_MASK(14, 1)
/* definitions for register: Hardware Feature Register */
/* definitions for field: Memory size in reg: Hardware Feature Register */
......
include/i2c.h
View file @ 3168c53e
......@@ -7,7 +7,10 @@
#define __I2C_H
uint8_t mi2c_devprobe(uint8_t i2cif, uint8_t i2c_addr);
uint8_t mi2c_poll(uint32_t time_out_ms); //ONLY for fmc i2c
void mi2c_init(uint8_t i2cif);
void mi2c_lock(void); //ONLY for fmc i2c
void mi2c_unlock(void); //ONLY for fmc i2c
void mi2c_start(uint8_t i2cif);
void mi2c_repeat_start(uint8_t i2cif);
void mi2c_stop(uint8_t i2cif);
......
include/syscon.h
View file @ 3168c53e
......@@ -52,15 +52,17 @@ struct SYSCON_WB {
};
/*GPIO pins*/
#define GPIO_LED_LINK SYSC_GPSR_LED_LINK
#define GPIO_LED_STAT SYSC_GPSR_LED_STAT
#define GPIO_BTN1 SYSC_GPSR_BTN1
#define GPIO_BTN2 SYSC_GPSR_BTN2
#define GPIO_SFP_DET SYSC_GPSR_SFP_DET
#define GPIO_SPI_SCLK SYSC_GPSR_SPI_SCLK
#define GPIO_SPI_NCS SYSC_GPSR_SPI_NCS
#define GPIO_SPI_MOSI SYSC_GPSR_SPI_MOSI
#define GPIO_SPI_MISO SYSC_GPSR_SPI_MISO
#define GPIO_LED_LINK SYSC_GPSR_LED_LINK
#define GPIO_LED_STAT SYSC_GPSR_LED_STAT
#define GPIO_BTN1 SYSC_GPSR_BTN1
#define GPIO_BTN2 SYSC_GPSR_BTN2
#define GPIO_SFP_DET SYSC_GPSR_SFP_DET
#define GPIO_SPI_SCLK SYSC_GPSR_SPI_SCLK
#define GPIO_SPI_NCS SYSC_GPSR_SPI_NCS
#define GPIO_SPI_MOSI SYSC_GPSR_SPI_MOSI
#define GPIO_SPI_MISO SYSC_GPSR_SPI_MISO
#define WRC_FMC_I2C_SEL SYSC_GPSR_FMC_SEL
#define WRC_FMC_I2C_LCK SYSC_GPSR_FMC_LCK
#define WRPC_FMC_I2C 0
#define WRPC_SFP_I2C 1
......
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