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Software for White Rabbit PTP Core
Commit 24da97e3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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include: migrate WDIAGS registers to Cheby + add a few more for the V2 diag block

parent 08b3a910
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include/hw/build_cheby.sh 0 → 100755
View file @ 24da97e3
cheby --gen-c wrc_diags_regs.h -i wrc_diags_regs.cheby
\ No newline at end of file
include/hw/wrc_diags_regs.cheby 0 → 100644
View file @ 24da97e3
memory-map:
name: wrc_diags
description: WR Core Diagnostics
comment: Diagnostics information accessible via WR
bus: wb-32-be
x-wbgen:
hdl_entity: wrc_diags_wb
version: 1
schema-version:
core: 2.0.0
x-conversions: 1.0.0
x-driver-edge: 1.0.0
x-enums: 1.0.0
x-fesa: 2.0.0
x-gena: 2.0.0
x-hdl: 1.0.0
x-map-info: 1.0.0
x-wbgen: 1.0.0
children:
- reg:
name: VER
description: Version register
width: 32
access: rw
address: 0x0
children:
- field:
name: ID
description: Version identifier
range: 31-0
preset: 0x1
- reg:
name: CTRL
description: Ctrl
width: 32
access: rw
address: 0x4
children:
- field:
name: DATA_VALID
description: WR DIAG data valid
comment: '0: valid\n 1:transcient'
range: 0
- field:
name: DATA_SNAPSHOT
description: WR DIAG data snapshot
comment: '1: snapshot data (data in registers will not change aveter VALID becomes true)'
range: 8
- reg:
name: WDIAG_SSTAT
description: 'WRPC Diag: servo status'
width: 32
access: ro
address: 0x8
children:
- field:
name: wr_mode
description: WR valid
comment: '0: not valid\n 1:valid'
range: 0
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: BIT
- field:
name: servostate
description: Servo State
comment: '0: Uninitialized\n 1: SYNC_NSEC\n 2: SYNC_TAI\n 3: SYNC_PHASE\n 4: TRACK_PHASE\n 5: WAIT_OFFSET_STABLE'
range: 11-8
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: SLV
- reg:
name: WDIAG_PSTAT
description: 'WRPC Diag: Port status'
width: 32
access: ro
address: 0xc
children:
- field:
name: link
description: Link Status
comment: '0: link down\n 1: link up'
range: 0
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: BIT
- field:
name: locked
description: PLL Locked
comment: '0: not locked\n 1: locked'
range: 1
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: BIT
- reg:
name: WDIAG_PTPSTAT
description: 'WRPC Diag: PTP state'
width: 32
access: ro
address: 0x10
children:
- field:
name: ptpstate
description: PTP State
comment: '0: NONE\n 1: PPS_INITIALIZING\n 2: PPS_FAULTY\n 3: disabled\n 4: PPS_LISTENING\n 5: PPS_PRE_MASTER\n 6: PPS_MASTER\n 7: PPS_PASSIVE\n 8: PPS_UNCALIBRATED\n 9: PPS_SLAVE\n 100-116: WR STATES\n see: ppsi/proto-ext-whiterabbit/wr-constants.h\n ppsi/include/ppsi/ieee1588_types.h'
range: 7-0
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: SLV
- reg:
name: WDIAG_ASTAT
description: 'WRPC Diag: AUX state'
width: 32
access: ro
address: 0x14
children:
- field:
name: aux
description: AUX channel
comment: 'A vector of bits, one bit per channel\n 0: not valid\n 1:valid'
range: 7-0
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
type: SLV
- reg:
name: WDIAG_TXFCNT
description: 'WRPC Diag: Tx PTP Frame cnts'
comment: Number of transmitted PTP Frames
width: 32
access: ro
address: 0x18
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_RXFCNT
description: 'WRPC Diag: Rx PTP Frame cnts'
comment: Number of received PTP Frames
width: 32
access: ro
address: 0x1c
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_SEC_MSB
description: 'WRPC Diag:local time [msb of s]'
comment: Local Time expressed in seconds since epoch (TAI)
width: 32
access: ro
address: 0x20
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_SEC_LSB
description: 'WRPC Diag: local time [lsb of s]'
comment: Local Time expressed in seconds since epoch (TAI)
width: 32
access: ro
address: 0x24
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_NS
description: 'WRPC Diag: local time [ns]'
comment: Nanoseconds part of the Local Time expressed in seconds since epoch (TAI)
width: 32
access: ro
address: 0x28
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_MU_MSB
description: 'WRPC Diag: Round trip (mu) [msb of ps]'
width: 32
access: ro
address: 0x2c
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_MU_LSB
description: 'WRPC Diag: Round trip (mu) [lsb of ps]'
width: 32
access: ro
address: 0x30
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_DMS_MSB
description: 'WRPC Diag: Master-slave delay (dms) [msb of ps]'
width: 32
access: ro
address: 0x34
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_DMS_LSB
description: 'WRPC Diag: Master-slave delay (dms) [lsb of ps]'
width: 32
access: ro
address: 0x38
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_ASYM
description: 'WRPC Diag: Total link asymmetry [ps]'
width: 32
access: ro
address: 0x3c
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_CKO
description: 'WRPC Diag: Clock offset (cko) [ps]'
width: 32
access: ro
address: 0x40
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_SETP
description: 'WRPC Diag: Phase setpoint (setp) [ps]'
width: 32
access: ro
address: 0x44
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_UCNT
description: 'WRPC Diag: Update counter (ucnt)'
width: 32
access: ro
address: 0x48
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_TEMP
description: 'WRPC Diag: Board temperature [C degree]'
width: 32
access: ro
address: 0x4c
x-wbgen:
access_bus: READ_ONLY
access_dev: WRITE_ONLY
field_description: Data
type: SLV
- reg:
name: WDIAG_AUX0_DETAIL_STAT
description: 'WRPC Diag: Aux0 detailed clock status'
width: 32
access: ro
address: 0x50
children:
- field:
name: PHASE
description: Phase (picoseconds)
range: 23-0
- field:
name: MODE
description: Mode (0 = PLL slave, 1 = phase monitor)
range: 25-24
- field:
name: ENABLED
description: Enabled
range: 26
- field:
name: LOCKED
description: Locked (or phase ready in case of phsae monitor mode)
range: 27
- reg:
name: WDIAG_AUX1_DETAIL_STAT
description: 'WRPC Diag: Aux1 detailed clock status'
width: 32
access: ro
address: 0x54
- reg:
name: WDIAG_AUX2_DETAIL_STAT
description: 'WRPC Diag: Aux2 detailed clock status'
width: 32
access: ro
address: 0x58
- reg:
name: WDIAG_AUX3_DETAIL_STAT
description: 'WRPC Diag: Aux3 detailed clock status'
width: 32
access: ro
address: 0x5c
- reg:
name: WDIAG_RX_ERR_CNT
description: 'WRPC Diag: RX Error count'
width: 32
access: ro
address: 0x60
- reg:
name: WDIAG_SERVO_UPTIME_MSB
description: 'WRPC Diag: Servo Up Timestamp (MSB)'
width: 32
access: ro
address: 0x64
- reg:
name: WDIAG_SERVO_UPTIME_LSB
description: 'WRPC Diag: Servo Up Timestamp (LSB)'
width: 32
access: ro
address: 0x68
- reg:
name: WDIAG_SERVO_RESTART_COUNT
description: 'WRPC Diag: Servo restart count'
width: 32
access: ro
address: 0x6c
\ No newline at end of file
include/hw/wrc_diags_regs.h
View file @ 24da97e3
This diff is collapsed.
include/hw/wrc_diags_regs_v1.h 0 → 100644
View file @ 24da97e3
#ifndef __WRC_DIAGS_REGS_V1_H
#define __WRC_DIAGS_REGS_V1_H
#include <stdint.h>
struct wrc_diags_regs_v1 {
/* [0x0]: REG Version register */
uint32_t VER;
/* [0x4]: REG Ctrl */
uint32_t CTRL;
/* [0x8]: REG WRPC Diag: servo status */
uint32_t WDIAG_SSTAT;
/* [0xc]: REG WRPC Diag: Port status */
uint32_t WDIAG_PSTAT;
/* [0x10]: REG WRPC Diag: PTP state */
uint32_t WDIAG_PTPSTAT;
/* [0x14]: REG WRPC Diag: AUX state */
uint32_t WDIAG_ASTAT;
/* [0x18]: REG WRPC Diag: Tx PTP Frame cnts */
uint32_t WDIAG_TXFCNT;
/* [0x1c]: REG WRPC Diag: Rx PTP Frame cnts */
uint32_t WDIAG_RXFCNT;
/* [0x20]: REG WRPC Diag:local time [msb of s] */
uint32_t WDIAG_SEC_MSB;
/* [0x24]: REG WRPC Diag: local time [lsb of s] */
uint32_t WDIAG_SEC_LSB;
/* [0x28]: REG WRPC Diag: local time [ns] */
uint32_t WDIAG_NS;
/* [0x2c]: REG WRPC Diag: Round trip (mu) [msb of ps] */
uint32_t WDIAG_MU_MSB;
/* [0x30]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
uint32_t WDIAG_MU_LSB;
/* [0x34]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
uint32_t WDIAG_DMS_MSB;
/* [0x38]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
uint32_t WDIAG_DMS_LSB;
/* [0x3c]: REG WRPC Diag: Total link asymmetry [ps] */
uint32_t WDIAG_ASYM;
/* [0x40]: REG WRPC Diag: Clock offset (cko) [ps] */
uint32_t WDIAG_CKO;
/* [0x44]: REG WRPC Diag: Phase setpoint (setp) [ps] */
uint32_t WDIAG_SETP;
/* [0x48]: REG WRPC Diag: Update counter (ucnt) */
uint32_t WDIAG_UCNT;
/* [0x4c]: REG WRPC Diag: Board temperature [C degree] */
uint32_t WDIAG_TEMP;
};
#endif
include/hw/wrc_syscon_regs.h
View file @ 24da97e3
......@@ -3,7 +3,7 @@
* File : wrc_syscon_regs.h
* Author : auto-generated by wbgen2 from wrc_syscon_wb.wb
* Created : Mon Nov 27 13:37:56 2017
* Created : Sat Jun 19 00:29:20 2021
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrc_syscon_wb.wb
......@@ -208,77 +208,6 @@
#define SYSC_DIAG_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: User Diag: data to read/write */
/* definitions for register: WRPC Diag: ctrl */
/* definitions for field: WR DIAG data valid in reg: WRPC Diag: ctrl */
#define SYSC_WDIAG_CTRL_DATA_VALID WBGEN2_GEN_MASK(0, 1)
/* definitions for field: WR DIAG data snapshot in reg: WRPC Diag: ctrl */
#define SYSC_WDIAG_CTRL_DATA_SNAPSHOT WBGEN2_GEN_MASK(8, 1)
/* definitions for register: WRPC Diag: servo status */
/* definitions for field: WR valid in reg: WRPC Diag: servo status */
#define SYSC_WDIAG_SSTAT_WR_MODE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Servo State in reg: WRPC Diag: servo status */
#define SYSC_WDIAG_SSTAT_SERVOSTATE_MASK WBGEN2_GEN_MASK(8, 4)
#define SYSC_WDIAG_SSTAT_SERVOSTATE_SHIFT 8
#define SYSC_WDIAG_SSTAT_SERVOSTATE_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define SYSC_WDIAG_SSTAT_SERVOSTATE_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for register: WRPC Diag: Port status */
/* definitions for field: Link Status in reg: WRPC Diag: Port status */
#define SYSC_WDIAG_PSTAT_LINK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PLL Locked in reg: WRPC Diag: Port status */
#define SYSC_WDIAG_PSTAT_LOCKED WBGEN2_GEN_MASK(1, 1)
/* definitions for register: WRPC Diag: PTP state */
/* definitions for field: PTP State in reg: WRPC Diag: PTP state */
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_MASK WBGEN2_GEN_MASK(0, 8)
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_SHIFT 0
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SYSC_WDIAG_PTPSTAT_PTPSTATE_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: WRPC Diag: AUX state */
/* definitions for field: AUX channel in reg: WRPC Diag: AUX state */
#define SYSC_WDIAG_ASTAT_AUX_MASK WBGEN2_GEN_MASK(0, 8)
#define SYSC_WDIAG_ASTAT_AUX_SHIFT 0
#define SYSC_WDIAG_ASTAT_AUX_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SYSC_WDIAG_ASTAT_AUX_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: WRPC Diag: Tx PTP Frame cnts */
/* definitions for register: WRPC Diag: Rx PTP Frame cnts */
/* definitions for register: WRPC Diag:local time [msb of s] */
/* definitions for register: WRPC Diag: local time [lsb of s] */
/* definitions for register: WRPC Diag: local time [ns] */
/* definitions for register: WRPC Diag: Round trip (mu) [msb of ps] */
/* definitions for register: WRPC Diag: Round trip (mu) [lsb of ps] */
/* definitions for register: WRPC Diag: Master-slave delay (dms) [msb of ps] */
/* definitions for register: WRPC Diag: Master-slave delay (dms) [lsb of ps] */
/* definitions for register: WRPC Diag: Total link asymmetry [ps] */
/* definitions for register: WRPC Diag: Clock offset (cko) [ps] */
/* definitions for register: WRPC Diag: Phase setpoint (setp) [ps] */
/* definitions for register: WRPC Diag: Update counter (ucnt) */
/* definitions for register: WRPC Diag: Board temperature [C degree] */
/* [0x0]: REG Syscon reset register */
#define SYSC_REG_RSTR 0x00000000
/* [0x4]: REG GPIO Set/Readback Register */
......@@ -303,42 +232,4 @@
#define SYSC_REG_DIAG_CR 0x00000028
/* [0x2c]: REG User Diag: data to read/write */
#define SYSC_REG_DIAG_DAT 0x0000002c
/* [0x30]: REG WRPC Diag: ctrl */
#define SYSC_REG_WDIAG_CTRL 0x00000030
/* [0x34]: REG WRPC Diag: servo status */
#define SYSC_REG_WDIAG_SSTAT 0x00000034
/* [0x38]: REG WRPC Diag: Port status */
#define SYSC_REG_WDIAG_PSTAT 0x00000038
/* [0x3c]: REG WRPC Diag: PTP state */
#define SYSC_REG_WDIAG_PTPSTAT 0x0000003c
/* [0x40]: REG WRPC Diag: AUX state */
#define SYSC_REG_WDIAG_ASTAT 0x00000040
/* [0x44]: REG WRPC Diag: Tx PTP Frame cnts */
#define SYSC_REG_WDIAG_TXFCNT 0x00000044
/* [0x48]: REG WRPC Diag: Rx PTP Frame cnts */
#define SYSC_REG_WDIAG_RXFCNT 0x00000048
/* [0x4c]: REG WRPC Diag:local time [msb of s] */
#define SYSC_REG_WDIAG_SEC_MSB 0x0000004c
/* [0x50]: REG WRPC Diag: local time [lsb of s] */
#define SYSC_REG_WDIAG_SEC_LSB 0x00000050
/* [0x54]: REG WRPC Diag: local time [ns] */
#define SYSC_REG_WDIAG_NS 0x00000054
/* [0x58]: REG WRPC Diag: Round trip (mu) [msb of ps] */
#define SYSC_REG_WDIAG_MU_MSB 0x00000058
/* [0x5c]: REG WRPC Diag: Round trip (mu) [lsb of ps] */
#define SYSC_REG_WDIAG_MU_LSB 0x0000005c
/* [0x60]: REG WRPC Diag: Master-slave delay (dms) [msb of ps] */
#define SYSC_REG_WDIAG_DMS_MSB 0x00000060
/* [0x64]: REG WRPC Diag: Master-slave delay (dms) [lsb of ps] */
#define SYSC_REG_WDIAG_DMS_LSB 0x00000064
/* [0x68]: REG WRPC Diag: Total link asymmetry [ps] */
#define SYSC_REG_WDIAG_ASYM 0x00000068
/* [0x6c]: REG WRPC Diag: Clock offset (cko) [ps] */
#define SYSC_REG_WDIAG_CKO 0x0000006c
/* [0x70]: REG WRPC Diag: Phase setpoint (setp) [ps] */
#define SYSC_REG_WDIAG_SETP 0x00000070
/* [0x74]: REG WRPC Diag: Update counter (ucnt) */
#define SYSC_REG_WDIAG_UCNT 0x00000074
/* [0x78]: REG WRPC Diag: Board temperature [C degree] */
#define SYSC_REG_WDIAG_TEMP 0x00000078
#endif
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