fixes to get wrc to boot with silabs/riscv on spec150t, wip

1e2001f1 · Tomasz Wlostowski · 32f4771f · 1e2001f1 · 1e2001f1 · 1e2001f1
Commit 1e2001f1 authored Apr 03, 2023 by Tomasz Wlostowski
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Showing with 33 additions and 21 deletions

Makefile Makefile +1 -1

board.h boards/spec_silabs/board.h +31 -19

endpoint.c dev/endpoint.c +1 -1

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--- a/Makefile
+++ b/Makefile
@@ -103,7 +103,7 @@ ldflags-$(CONFIG_ARCH_LM32) = -mmultiply-enabled -mbarrel-shift-enabled \
 	-nostdlib -T $(LDS-y)
 ldflags-$(CONFIG_ARCH_RISCV) = -march=rv32im$(USE-COMP-INSTR-y) -mabi=ilp32 \
 	-nostdlib -T $(LDS-y)
-asflags-$(CONFIG_ARCH_RISCV) += -march=rv32im$(USE-COMP-INSTR-y) -mabi=ilp32
+asflags-$(CONFIG_ARCH_RISCV) += -march=rv32im$(USE-COMP-INSTR-y)_zicsr -mabi=ilp32
 arch-files-$(CONFIG_ARCH_LM32) = $(OUTPUT).bram $(OUTPUT).vhd $(OUTPUT).mif
 arch-files-$(CONFIG_ARCH_RISCV) = $(OUTPUT).bram $(OUTPUT).vhd $(OUTPUT).mif


--- a/boards/spec_silabs/board.h
+++ b/boards/spec_silabs/board.h
@@ -3,25 +3,34 @@
 *
 * Released according to the GNU GPL, version 2 or any later version.
 */
+
+#include <netconsole.h>
+
 #ifndef __BOARD_WRC_H
 #define __BOARD_WRC_H
-
 /*
 * This is meant to be automatically included by the Makefile,
 * when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch)
 */

+#ifdef CONFIG_ARCH_RISCV
+#define DEV_BASE	0x100000
+#elif defined CONFIG_ARCH_LM32
+#define DEV_BASE	0x40000
+#else
+#error (Wrong Arch!)
+#endif
+
 /* Fixed base addresses */
-#define BASE_MINIC	0x20000
-#define BASE_EP		0x20100
-#define BASE_SOFTPLL 	0x20200
-#define BASE_PPS_GEN 	0x20300
-#define BASE_SYSCON	0x20400
-#define BASE_UART	0x20500
-#define BASE_ONEWIRE	0x20600
-#define BASE_SI57X_INTERFACE	0x28000
-#define BASE_WDIAGS_PRIV	0x20900
-#define BOARD_USE_EVENTS 0
+#define BASE_MINIC		(DEV_BASE + 0x000)
+#define BASE_EP			(DEV_BASE + 0x100)
+#define BASE_SOFTPLL		(DEV_BASE + 0x200)
+#define BASE_PPS_GEN 		(DEV_BASE + 0x300)
+#define BASE_SYSCON		(DEV_BASE + 0x400)
+#define BASE_UART		(DEV_BASE + 0x500)
+#define BASE_ONEWIRE		(DEV_BASE + 0x600)
+#define BASE_WDIAGS_PRIV       	(DEV_BASE + 0x900)
+#define BASE_SI57X_INTERFACE	(DEV_BASE + 0x8000)

 /* Board-specific parameters */
 #define TICS_PER_SECOND 1000
@@ -29,13 +38,16 @@
 /* WR Core system/CPU clock frequency in Hz */
 #define CPU_CLOCK 62500000ULL

-
+/* WR Reference clock period (picoseconds) and frequency (Hz) */
+#ifdef CONFIG_TARGET_GENERIC_PHY_16BIT
+#  define NS_PER_CLOCK 16
+#  define REF_CLOCK_PERIOD_PS 16000
+#  define REF_CLOCK_FREQ_HZ 62500000
+#else
 #  define NS_PER_CLOCK 8
 #  define REF_CLOCK_PERIOD_PS 8000
 #  define REF_CLOCK_FREQ_HZ 125000000
-
-/* Baud rate of the builtin UART (does not apply to the VUART) */
-#define UART_BAUDRATE 115200ULL
+#endif

 /* Maximum number of simultaneously created sockets */
 #define NET_MAX_SOCKETS 12
@@ -56,13 +68,13 @@
 #define BOARD_MAX_CHAN_AUX		2
 #define BOARD_MAX_PTRACKERS		1

-#define CONFIG_DISALLOW_LONG_DIVISION
+#undef CONFIG_DISALLOW_LONG_DIVISION

-#define BOARD_MAX_CONSOLE_DEVICES 1
+#define BOARD_USE_EVENTS 0

-#define CONSOLE_UART_BAUDRATE 115200
+#define BOARD_MAX_CONSOLE_DEVICES (1 + HAS_NETCONSOLE + HAS_PUTS_SYSLOG)

-#define SDB_ADDRESS 0x30000
+#define CONSOLE_UART_BAUDRATE 115200

 #define FMC_EEPROM_ADR 0x50


--- a/dev/endpoint.c
+++ b/dev/endpoint.c
@@ -101,7 +101,7 @@ void ep_reset_phy(struct wr_endpoint_device* dev)
 	ep_pcs_write(dev, MDIO_REG_MCR, MDIO_MCR_PDOWN);	/* reset the PHY */
 	
 	pp_printf("Running long PHY reset...\n");
-	timer_delay_ms(10000);
+	timer_delay_ms(300);
 	pp_printf("PHY reset complete\n");
 	ep_pcs_write(dev, MDIO_REG_MCR, MDIO_MCR_RESET);	/* reset the PHY */
 	ep_pcs_write(dev, MDIO_REG_MCR, 0);	/* reset the PHY */