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Software for White Rabbit PTP Core
Commit 02f04ab1 authored by Jose Lopez's avatar Jose Lopez
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working main AD9516 for new ljd switch

parent 6174a3db
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Showing with 180 additions and 75 deletions
dev/ad9516.c
View file @ 02f04ab1
......@@ -243,8 +243,8 @@ int ext_ad9516_locked (void)
int ad9516_init(int scb_version)
{
pp_printf("Initializing AD9516 PLL...\n");
pp_printf("Initializing AD9516 PLL...\n");
oc_spi_init((void *)BASE_SPI);
void *spi_base = (void *)BASE_SPI;
......@@ -266,23 +266,29 @@ int ad9516_init(int scb_version)
return -1;
}
if( scb_version >= 34) //New SCB v3.4. 10MHz Output.
pp_printf("PLL Responding\n");
if( scb_version >= 34){ //New SCB v3.4. 10MHz Output.
ad9516_load_regset(spi_base, ad9516_base_config_34, ARRAY_SIZE(ad9516_base_config_34), 0);
else //Old one
pp_printf("loaded for 34\n");
}
else{ //Old one
ad9516_load_regset(spi_base, ad9516_base_config_33, ARRAY_SIZE(ad9516_base_config_33), 0);
pp_printf("loaded for 33\n");
}
ad9516_load_regset(spi_base, ad9516_ref_tcxo, ARRAY_SIZE(ad9516_ref_tcxo), 1);
pp_printf("Did the weird rewrite\n");
ad9516_wait_lock(spi_base);
ad9516_sync_outputs(spi_base);
if( scb_version >= 34) { //New SCB v3.4. 10MHz Output.
ad9516_set_output_divider(spi_base, 2, 4, 0); // OUT2. 187.5 MHz. - not anymore
ad9516_set_output_divider(spi_base, 3, 4, 0); // OUT3. 187.5 MHz. - not anymore
// ad9516_set_output_divider(spi_base, 2, 4, 0); // OUT2. 187.5 MHz. - not anymore
// ad9516_set_output_divider(spi_base, 3, 4, 0); // OUT3. 187.5 MHz. - not anymore
ad9516_set_output_divider(spi_base, 4, 1, 0); // OUT4. 500 MHz.
ad9516_set_output_divider(spi_base, 9, 20,0);
// ad9516_set_output_divider(spi_base, 4, 1, 0); // OUT4. 500 MHz.
// ad9516_set_output_divider(spi_base, 9, 20,0);
/*The following PLL outputs have been configured through the ad9516_base_config_34 register,
* so it doesn't need to replicate the configuration:
......@@ -301,8 +307,9 @@ int ad9516_init(int scb_version)
}
ad9516_sync_outputs(spi_base);
ad9516_set_vco_divider(spi_base, 3);
ad9516_set_vco_divider(spi_base, 6);
pp_printf("Reg for clk8 has value %d\n",ad9516_read_reg(spi_base,0x142));
pp_printf("AD9516 locked.\n");
gpio_out(GPIO_SYS_CLK_SEL, 1); /* switch the system clock to the PLL reference */
......
dev/ad9516_config.h
View file @ 02f04ab1
......@@ -6,6 +6,76 @@ const struct ad9516_reg ad9516_base_config_33[] = {
{0x0002, 0x10},
{0x0003, 0xC3},
{0x0004, 0x00},
{0x0010, 0x7D},
{0x0011, 0x05},
{0x0012, 0x00},
{0x0013, 0x06},
{0x0014, 0x09},
{0x0015, 0x00},
{0x0016, 0x05},
{0x0017, 0x88},
{0x0018, 0x07},
{0x0019, 0x00},
{0x001A, 0x00},
{0x001B, 0x00},
{0x001C, 0x82},
{0x001D, 0x00},
{0x001E, 0x00},
{0x001F, 0x0E},
{0x00A0, 0x01},
{0x00A1, 0x00},
{0x00A2, 0x25},
{0x00A3, 0x01},
{0x00A4, 0x00},
{0x00A5, 0x00},
{0x00A6, 0x01},
{0x00A7, 0x00},
{0x00A8, 0x00},
{0x00A9, 0x01},
{0x00AA, 0x00},
{0x00AB, 0x00},
{0x00F0, 0x08},
{0x00F1, 0x08},
{0x00F2, 0x08},
{0x00F3, 0x08},
{0x00F4, 0x08},
{0x00F5, 0x08},
{0x0140, 0x42},
{0x0141, 0x42},
{0x0142, 0x42},
{0x0143, 0x4E},
{0x0190, 0x11},
{0x0191, 0x00},
{0x0192, 0x00},
{0x0193, 0x11},
{0x0194, 0x00},
{0x0195, 0x00},
{0x0196, 0x11},
{0x0197, 0x00},
{0x0198, 0x00},
{0x0199, 0x11},
{0x019A, 0x00},
{0x019B, 0x21},
{0x019C, 0x20},
{0x019D, 0x00},
{0x019E, 0x11},
{0x019F, 0x00},
{0x01A0, 0x21},
{0x01A1, 0x20},
{0x01A2, 0x00},
{0x01A3, 0x00},
{0x01E0, 0x04},
{0x01E1, 0x02},
{0x0230, 0x00},
{0x0231, 0x00},
};
/* Configuration for the SCB version greater than or equal 3.4: Base + 6, 7, 8, 9 outputs*/
const struct ad9516_reg ad9516_base_config_34[] = {
{0x0000, 0x99},
{0x0001, 0x00},
{0x0002, 0x10},
{0x0003, 0xC3},
{0x0004, 0x00},
{0x0010, 0x7C},
{0x0011, 0x05},
{0x0012, 0x00},
......@@ -34,23 +104,24 @@ const struct ad9516_reg ad9516_base_config_33[] = {
{0x00A9, 0x01},
{0x00AA, 0x00},
{0x00AB, 0x00},
{0x00F0, 0x0A},
{0x00F1, 0x0A},
{0x00F2, 0x0A},
{0x00F3, 0x0A},
{0x00F0, 0x08},
{0x00F1, 0x08},
{0x00F2, 0x08},
{0x00F3, 0x08},
{0x00F4, 0x08},
{0x00F5, 0x08},
{0x0140, 0x43},
// The following registers configure the PLL outputs from 6 to 9.
{0x0140, 0x42},
{0x0141, 0x42},
{0x0142, 0x43},
{0x0143, 0x42},
{0x0190, 0x00},
{0x0191, 0x80},
{0x0142, 0x42},
{0x0143, 0x4E},
{0x0190, 0x11},
{0x0191, 0x00},
{0x0192, 0x00},
{0x0193, 0xBB},
{0x0193, 0x11},
{0x0194, 0x00},
{0x0195, 0x00},
{0x0196, 0x00},
{0x0196, 0x11},
{0x0197, 0x00},
{0x0198, 0x00},
{0x0199, 0x11},
......@@ -64,6 +135,7 @@ const struct ad9516_reg ad9516_base_config_33[] = {
{0x01A1, 0x20},
{0x01A2, 0x00},
{0x01A3, 0x00},
//
{0x01E0, 0x04},
{0x01E1, 0x02},
{0x0230, 0x00},
......@@ -71,20 +143,20 @@ const struct ad9516_reg ad9516_base_config_33[] = {
};
/* Configuration for the SCB version greater than or equal 3.4: Base + 6, 7, 8, 9 outputs*/
const struct ad9516_reg ad9516_base_config_34[] = {
{0x0000, 0x99},
const struct ad9516_reg ad9516_base_config_34_new[] = {
{0x0000, 0x18},
{0x0001, 0x00},
{0x0002, 0x10},
{0x0003, 0xC3},
{0x0004, 0x00},
{0x0010, 0x7C},
{0x0011, 0x04},
{0x0011, 0x05},
{0x0012, 0x00},
{0x0013, 0x0C},
{0x0014, 0x12},
{0x0013, 0x00},
{0x0014, 0x0B},
{0x0015, 0x00},
{0x0016, 0x05},
{0x0017, 0x88},
{0x0017, 0x00},
{0x0018, 0x07},
{0x0019, 0x00},
{0x001A, 0x00},
......@@ -105,32 +177,32 @@ const struct ad9516_reg ad9516_base_config_34[] = {
{0x00A9, 0x01},
{0x00AA, 0x00},
{0x00AB, 0x00},
{0x00F0, 0x0A},
{0x00F1, 0x0A},
{0x00F2, 0x0A},
{0x00F3, 0x0A},
{0x00F0, 0x08},
{0x00F1, 0x08},
{0x00F2, 0x08},
{0x00F3, 0x08},
{0x00F4, 0x08},
{0x00F5, 0x08},
// The following registers configure the PLL outputs from 6 to 9.
{0x0140, 0x42},
{0x0141, 0x42},
{0x0142, 0x43},
{0x0143, 0x4E},
{0x0190, 0x55},
{0x0142, 0x42},
{0x0143, 0x4A},
{0x0190, 0x11},
{0x0191, 0x00},
{0x0192, 0x00},
{0x0193, 0x11},
{0x0194, 0x00},
{0x0195, 0x00},
{0x0196, 0x10},
{0x0196, 0x11},
{0x0197, 0x00},
{0x0198, 0x00},
{0x0199, 0x33},
{0x0199, 0x11},
{0x019A, 0x00},
{0x019B, 0x11},
{0x019C, 0x20},
{0x019D, 0x00},
{0x019E, 0x33},
{0x019E, 0x11},
{0x019F, 0x00},
{0x01A0, 0x11},
{0x01A1, 0x20},
......@@ -144,27 +216,26 @@ const struct ad9516_reg ad9516_base_config_34[] = {
};
/* Configuration for the SCB version greater than or equal 3.4: Base + 6, 7, 8, 9 outputs*/
const struct ad9516_reg ad9516_ext_base_config[] = {
{0x0000, 0x99},
{0x0000, 0x18},
{0x0001, 0x00},
{0x0002, 0x10},
{0x0003, 0xC3},
{0x0004, 0x00},
{0x0010, 0x4C},
{0x0011, 0x00},
{0x0012, 0x00},
{0x0013, 0x06},
{0x0014, 0x12},
{0x0010, 0x7C},
{0x0011, 0x05},
{0x0012, 0x00},
{0x0013, 0x00},
{0x0014, 0x0B},
{0x0015, 0x00},
{0x0016, 0x04},
{0x0016, 0x05},
{0x0017, 0x00},
{0x0018, 0x07},
{0x0019, 0x00},
{0x001A, 0x00},
{0x001B, 0x00},
{0x001C, 0x01},
{0x001C, 0x02},
{0x001D, 0x00},
{0x001E, 0x00},
{0x001F, 0x0E},
......@@ -180,47 +251,48 @@ const struct ad9516_reg ad9516_ext_base_config[] = {
{0x00A9, 0x01},
{0x00AA, 0x00},
{0x00AB, 0x00},
{0x00F0, 0x0A},
{0x00F1, 0x0A},
{0x00F2, 0x0A},
{0x00F3, 0x0A},
{0x00F0, 0x08},
{0x00F1, 0x08},
{0x00F2, 0x08},
{0x00F3, 0x08},
{0x00F4, 0x08},
{0x00F5, 0x08},
// The following registers configure the PLL outputs from 6 to 9.
{0x0140, 0x42},
{0x0141, 0x42},
{0x0142, 0x08},
{0x0143, 0x4E},
{0x0190, 0x55},
{0x0142, 0x42},
{0x0143, 0x4A},
{0x0190, 0x11},
{0x0191, 0x00},
{0x0192, 0x00},
{0x0193, 0x11},
{0x0194, 0x00},
{0x0195, 0x00},
{0x0196, 0x10},
{0x0196, 0x11},
{0x0197, 0x00},
{0x0198, 0x00},
{0x0199, 0x33},
{0x0199, 0x11},
{0x019A, 0x00},
{0x019B, 0x11},
{0x019C, 0x20},
{0x019D, 0x00},
{0x019E, 0x33},
{0x019E, 0x11},
{0x019F, 0x00},
{0x01A0, 0x11},
{0x01A1, 0x20},
{0x01A2, 0x00},
{0x01A3, 0x00},
//
{0x01E0, 0x01},
{0x01E0, 0x02},
{0x01E1, 0x02},
{0x0230, 0x00},
{0x0231, 0x00},
};
/* Config for 25 MHz VCTCXO reference (RDiv = 5, use REF1) */
const struct ad9516_reg ad9516_ref_tcxo[] = {
{0x0011, 0x04},
{0x0011, 0x0A},
{0x0012, 0x00}, /* RDiv = 4 */
{0x001C, 0x06} /* Use REF1 */
};
......
softpll/softpll_ng.c
View file @ 02f04ab1
......@@ -162,7 +162,8 @@ static inline void sequencing_fsm(struct softpll_state *s, int tag_value, int ta
case SEQ_START_MAIN:
{
mpll_start(&s->mpll);
if(s->mode != SPLL_MODE_GRAND_MASTER)
mpll_start(&s->mpll);
s->seq_state = SEQ_WAIT_MAIN;
break;
}
......@@ -312,7 +313,8 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
helper_ref = spll_n_chan_ref; // Master/GM mode: lock the helper to the local ref clock
helper_init(&s->helper, helper_ref);
mpll_init(&s->mpll, slave_ref_channel, spll_n_chan_ref);
if (mode != SPLL_MODE_GRAND_MASTER)
mpll_init(&s->mpll, slave_ref_channel, spll_n_chan_ref);
for (i = 0; i < spll_n_chan_out - 1; i++) {
mpll_init(&s->aux[i].pll.dmtd, slave_ref_channel, spll_n_chan_ref + i + 1);
......@@ -463,12 +465,12 @@ void spll_show_stats()
if (softpll.mode > 0)
pp_printf("softpll: irqs %d seq %s mode %d "
"alignment_state %d HL%d ML%d HY=%d MY=%d DelCnt=%d setpoint:%d\n",
"alignment_state %d HL%d ML%d HY=%d MY=%d EM=%d setpoint:%d\n",
s->irq_count, stringlist_lookup(seq_states, s->seq_state),
s->mode, s->ext.align_state,
s->helper.ld.locked, s->mpll.ld.locked,
s->helper.pi.y, s->mpll.pi.y,
s->delock_count, s->mpll.phase_shift_current);
s->mpll.pi.x, s->mpll.phase_shift_current);
}
int spll_shifter_busy(int channel)
......
softpll/spll_common.c
View file @ 02f04ab1
......@@ -17,6 +17,10 @@
int pi_update(spll_pi_t *pi, int x)
{
int i_new, y;
if(x > ( (1 << TAG_BITS) - 100000 ) ){
x -= (1 <<TAG_BITS);
}
pi->x = x;
i_new = pi->integrator + x;
......@@ -27,12 +31,12 @@ int pi_update(spll_pi_t *pi, int x)
out of range and the output is going further away from
y_min/y_max. */
if (y < pi->y_min) {
y = pi->y_min;
// y = pi->y_min;
if ((pi->anti_windup && (i_new > pi->integrator))
|| !pi->anti_windup)
pi->integrator = i_new;
} else if (y > pi->y_max) {
y = pi->y_max;
// y = pi->y_max;
if ((pi->anti_windup && (i_new < pi->integrator))
|| !pi->anti_windup)
pi->integrator = i_new;
......
softpll/spll_main.c
View file @ 02f04ab1
......@@ -20,6 +20,7 @@
#undef WITH_SEQUENCING
void mpll_init(struct spll_main_state *s, int id_ref,
int id_out)
{
......@@ -29,8 +30,8 @@ void mpll_init(struct spll_main_state *s, int id_ref,
s->pi.anti_windup = 1;
s->pi.bias = 30000;
#if defined(CONFIG_WR_SWITCH)
s->pi.kp = 2000; // / 2;
s->pi.ki = 15; // / 2;
s->pi.kp = 1000; // / 2;
s->pi.ki = 5; // / 2;
#elif defined(CONFIG_WR_NODE)
s->pi.kp = -1100; // / 2;
s->pi.ki = -30; // / 2;
......@@ -52,6 +53,7 @@ void mpll_init(struct spll_main_state *s, int id_ref,
pi_init((spll_pi_t *)&s->pi);
ld_init((spll_lock_det_t *)&s->ld);
}
void mpll_start(struct spll_main_state *s)
......@@ -74,6 +76,7 @@ void mpll_start(struct spll_main_state *s)
pi_init((spll_pi_t *)&s->pi);
ld_init((spll_lock_det_t *)&s->ld);
spll_enable_tagger(s->id_ref, 1);
spll_enable_tagger(s->id_out, 1);
spll_debug(DBG_EVENT | DBG_MAIN, DBG_EVT_START, 1);
......@@ -99,8 +102,10 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
s->tag_out = tag;
if (s->tag_ref >= 0) {
if(s->tag_ref_d >= 0 && s->tag_ref_d > s->tag_ref)
s->adder_ref += (1 << TAG_BITS);
if(s->tag_ref_d >= 0 && s->tag_ref_d > s->tag_ref){
s->adder_ref += (1 << TAG_BITS);
}
s->tag_ref_d = s->tag_ref;
}
......@@ -108,13 +113,18 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
if (s->tag_out >= 0) {
if(s->tag_out_d >= 0 && s->tag_out_d > s->tag_out)
s->adder_out += (1 << TAG_BITS);
s->adder_out += (1 << TAG_BITS);
s->tag_out_d = s->tag_out;
}
if (s->tag_ref >= 0 && s->tag_out >= 0) {
err = s->adder_ref + s->tag_ref - s->adder_out - s->tag_out;
// if (!(count++ % 1000))
// {
// pll_verbose("%d %d %d %d %d %d\n",count,s->tag_ref,s->tag_out,s->adder_ref,s->adder_out,err);
// }
#ifndef WITH_SEQUENCING
......@@ -135,12 +145,17 @@ int mpll_update(struct spll_main_state *s, int tag, int source)
#endif
if (err > ((1 << TAG_BITS) - (1 << HPLL_N)))
{
err -= (1 << TAG_BITS);
}
y = pi_update((spll_pi_t *)&s->pi, err);
SPLL->DAC_MAIN = SPLL_DAC_MAIN_VALUE_W(y)
| SPLL_DAC_MAIN_DAC_SEL_W(s->dac_index);
spll_debug(DBG_MAIN | DBG_REF, s->tag_ref + s->adder_ref, 0);
spll_debug(DBG_MAIN | DBG_TAG, s->tag_out + s->adder_out, 0);
spll_debug(DBG_MAIN | DBG_REF, s->tag_ref, 0); // + s->adder_ref, 0);
spll_debug(DBG_MAIN | DBG_TAG, s->tag_out, 0); // + s->adder_out, 0);
spll_debug(DBG_MAIN | DBG_ERR, err, 0);
spll_debug(DBG_MAIN | DBG_SAMPLE_ID, s->sample_n++, 0);
spll_debug(DBG_MAIN | DBG_Y, y, 1);
......
wrs_main.c
View file @ 02f04ab1
......@@ -17,7 +17,7 @@
#include "ext-board.h"
int scb_ver = 33; /* SCB version */
int scb_ver = 34; /* SCB version */
extern struct spll_stats stats;
......@@ -42,9 +42,9 @@ int main(void)
build_revision, build_date, build_time);
pp_printf("SCB version: %d. %s\n", scb_ver,(scb_ver>=34)?"10 MHz SMC Output.":"" );
pp_printf("Start counter %d\n", stats.start_cnt);
if (gpio_in(GPIO_EXT_BOARD_DETECT))
pp_printf("\n--- WRS Low jitter board detected. ---\nAllow 1 hour of warming up before starting measurements\n");
pp_printf("--\n");
//if (gpio_in(GPIO_EXT_BOARD_DETECT))
// pp_printf("\n--- WRS Low jitter board detected. ---\nAllow 1 hour of warming up before starting measurements\n");
//pp_printf("--\n");
if (stats.start_cnt > 1) {
pp_printf("!!spll does not work after restart!!\n");
......@@ -65,6 +65,11 @@ int main(void)
start_tics = tics;
}
/* if (time_after(tics, start_tics + TICS_PER_SECOND*10)){
if
}
*/
rts_update();
rtipc_action();
spll_update();
......
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