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Notes: - no PPS divider phase alignment (yet) - works on the SPEC's Si570 @ 100 MHz (4/5 freq ratio) - very untested! consider it a proof of concept. - requires updated VHDL (see wr-cores with the same branch name) - improve debug tag header encoding prevent AUX clock FSM from getting stuck when the first locking attempt is unsuccessful. Also hack to fix the frequency/phase regulation mode threshold - to be exposed through api
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