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wr2rf-vme
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DAC clock - AC coupling
#32
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
critical
hw
CLOSED
9
updated
Jun 30, 2020
DC coupling for FPGA clock ECL to LVDS
#31
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
5
updated
Jun 25, 2020
Trigger unit output glitches
#30
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
9
updated
Jun 16, 2020
wire length matching
#29
· opened
May 13, 2020
by
Tristan Gingold
Schematic done
hw
minor
CLOSED
4
updated
Jun 17, 2020
FPGA configuration IO
#28
· opened
May 13, 2020
by
Gregoire Hagmann
Schematic done
hdl
hw
important
xdc update
CLOSED
2
updated
Jun 29, 2020
consider using an INA240 for the OCXO current sense
#27
· opened
May 12, 2020
by
Christos Gentsos
Schematic done
hw
minor
CLOSED
2
updated
Jun 10, 2020
1V0 LDO current sharing scheme - questions
#26
· opened
May 12, 2020
by
Christos Gentsos
Schematic done
hw
question
CLOSED
8
updated
Jun 16, 2020
Front panel Timing I/O
#25
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
important
CLOSED
2
updated
Jun 24, 2020
Front panel connections
#24
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
5
updated
Jul 07, 2020
RF trigger output
#23
· opened
May 12, 2020
by
Gregoire Hagmann
Schematic done
hw
question
CLOSED
6
updated
Jul 07, 2020
incorrect note about LTC5598IUF#PBF
#22
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
hw
CLOSED
2
updated
Jun 06, 2020
pulse shaper - questions
#21
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
hw
question
CLOSED
11
updated
Jun 10, 2020
pulse shaper - vcc connected to vin
#20
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
critical
hw
CLOSED
1
updated
May 12, 2020
Inconsistent pull-down for VME_RETRY_OE and VME_A_OE_N
#19
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
hw
question
CLOSED
1
updated
Jun 08, 2020
could remove VME_A_DIR and VME_LWORD_N
#18
· opened
May 12, 2020
by
Tristan Gingold
Schematic done
cosmetics
hw
CLOSED
1
updated
Jun 08, 2020
Faster buffers for front panel I/O
#17
· opened
May 11, 2020
by
Tom Levens
Schematic done
hdl
hw
important
xdc update
CLOSED
7
updated
Jun 29, 2020
Address switch
#16
· opened
May 11, 2020
by
Tom Levens
Schematic done
hdl
hw
minor
xdc update
CLOSED
4
updated
Jun 29, 2020
VME connector issues
#15
· opened
May 11, 2020
by
Tom Levens
Schematic done
hw
CLOSED
1
updated
Jun 06, 2020
Name change for NETs: CLK_FPGA_62M5_p and CLK_FPGA_62M5_p
#14
· opened
May 06, 2020
by
John Gill
Schematic done
hdl
hw
minor
CLOSED
3
updated
Jun 08, 2020
Solve wr-cores dependency
#13
· opened
Apr 27, 2020
by
Dimitris Lampridis
hdl
important
CLOSED
3
updated
Jun 09, 2020
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