submodule rejig

dda5a3e0 · John Gill · 7f630477 · dda5a3e0
Commit dda5a3e0 authored Mar 07, 2023 by John Gill
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.gitmodules .gitmodules +4 -4

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--- a/.gitmodules
+++ b/.gitmodules
@@ -6,7 +6,7 @@
 	url = https://ohwr.org/project/vme64x-core.git
 [submodule "dependencies/EDA-03072-V2-1-CTUasVTU"]
 	path = dependencies/EDA-03072-V2-1-CTUasVTU
-	url = ssh://git@gitlab.cern.ch:7999/BE-RF-PLDesign/General/EDA-03072-V2-1-CTUasVTU.git
+	url = https://gitlab.cern.ch/BE-RF-PLDesign/General/EDA-03072-V2-1-CTUasVTU.git
 [submodule "dependencies/wr-cores"]
 	path = dependencies/wr-cores
 	url = https://ohwr.org/project/wr-cores.git
@@ -25,6 +25,6 @@
 [submodule "dependencies/nonIQModInterp2FIR"]
 	path = dependencies/nonIQModInterp2FIR
 	url = https://gitlab.cern.ch/jgill/nonIQModInterp2FIR.git
-[submodule "dependencies/stdinfo"]
-	path = dependencies/stdinfo
-	url = ssh://git@gitlab.cern.ch:7999/BE-RF-PLDesign/memorymaps/stdinfo.git
+[submodule "dependencies/RFNCO/MemMap/stdInfo"]
+	path = dependencies/RFNCO/MemMap/stdInfo
+	url = https://gitlab.cern.ch/BE-RF-PLDesign/memorymaps/stdinfo.git