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wr2rf-vme
Commits
b975ebcf
Commit
b975ebcf
authored
May 08, 2023
by
Tristan Gingold
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registers: add new registers
parent
b5355947
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3 changed files
with
65 additions
and
15 deletions
+65
-15
trigunit_regs.cheby
hdl/rtl/registers/trigunit_regs.cheby
+28
-8
wr2rf_ctrl_regs.cheby
hdl/rtl/registers/wr2rf_ctrl_regs.cheby
+30
-7
wr2rf_init_regs.cheby
hdl/rtl/registers/wr2rf_init_regs.cheby
+7
-0
No files found.
hdl/rtl/registers/trigunit_regs.cheby
View file @
b975ebcf
...
@@ -29,11 +29,22 @@ memory-map:
...
@@ -29,11 +29,22 @@ memory-map:
- field:
- field:
name: started
name: started
description: VTU is started, waiting for sync
description: VTU is started, waiting for sync
range:
9
range:
14
- field:
- field:
name: idle
name: idle
description: VTU is idle, waiting for a start
description: VTU is idle, waiting for a start
range: 8
range: 13
- field:
name: running
description: VTU core running
range: 12
- field:
name: missIdle
comment: Start ignored as VTU already running
description: >
The start pulse has been ignored because the VTU is already
running.
range: 10
- field:
- field:
name: missValid
name: missValid
comment: Start ignored as no configuration parameters
comment: Start ignored as no configuration parameters
...
@@ -42,7 +53,7 @@ memory-map:
...
@@ -42,7 +53,7 @@ memory-map:
the parameters were not valid. The configOffline.valid bit
the parameters were not valid. The configOffline.valid bit
was set to 0 when the pulse arrived. Changed when the next
was set to 0 when the pulse arrived. Changed when the next
start pulse is detected.
start pulse is detected.
range:
7
range:
9
- field:
- field:
name: missReady
name: missReady
comment: Start ignored as VTU not ready
comment: Start ignored as VTU not ready
...
@@ -51,7 +62,7 @@ memory-map:
...
@@ -51,7 +62,7 @@ memory-map:
it wasn't ready. Either the RF clock was not present, or
it wasn't ready. Either the RF clock was not present, or
the start pulse came too early. Changed when the next
the start pulse came too early. Changed when the next
start pulse is detected.
start pulse is detected.
range:
6
range:
8
- field:
- field:
name: startReady
name: startReady
comment: The VTU is ready to accept the start pulse
comment: The VTU is ready to accept the start pulse
...
@@ -59,10 +70,6 @@ memory-map:
...
@@ -59,10 +70,6 @@ memory-map:
Should be 1. Set to 0 when a start pulse has been detected
Should be 1. Set to 0 when a start pulse has been detected
and not yet transfered to the VTU. If stuck to 0, there is
and not yet transfered to the VTU. If stuck to 0, there is
no RF clock.
no RF clock.
range: 5
- field:
name: running
description: VTU core running
range: 4
range: 4
- field:
- field:
name: wrongBvalue
name: wrongBvalue
...
@@ -76,6 +83,19 @@ memory-map:
...
@@ -76,6 +83,19 @@ memory-map:
name: wrongWvalue
name: wrongWvalue
description: Wrong W value for the current mode
description: Wrong W value for the current mode
range: 1
range: 1
- reg:
name: config
description: Configuration registers
width: 16
access: rw
x-fesa:
persistence: None
children:
- field:
name: forceValidOffline
description: Consider offline values as always valid
range: 0
preset: 0
- reg:
- reg:
name: control
name: control
description: Control signals
description: Control signals
...
...
hdl/rtl/registers/wr2rf_ctrl_regs.cheby
View file @
b975ebcf
...
@@ -185,10 +185,33 @@ memory-map:
...
@@ -185,10 +185,33 @@ memory-map:
preset: 0x0
preset: 0x0
x-hdl:
x-hdl:
type: autoclear
type: autoclear
- reg:
name: gbl_status
description: Global status register, write to clear.
access: rw
width: 16
children:
- field:
name: rf1_t1_start
description: rf1/t1 has started
range: 0
x-hdl:
type: or-clr
- field:
name: rf1_t2_start
description: rf1/t2 has started
range: 1
x-hdl:
type: or-clr
- field:
name: rf2_t1_start
description: rf2/t1 has started
range: 2
x-hdl:
type: or-clr
- field:
name: rf2_t2_start
description: rf2/t2 has started
range: 3
x-hdl:
type: or-clr
hdl/rtl/registers/wr2rf_init_regs.cheby
View file @
b975ebcf
...
@@ -819,6 +819,13 @@ memory-map:
...
@@ -819,6 +819,13 @@ memory-map:
size: 64
size: 64
x-hdl:
x-hdl:
busgroup: True
busgroup: True
- submap:
name: xadc
interface: wb-16
description: Xilinx ADC
size: 256
x-hdl:
busgroup: True
- submap:
- submap:
name: wrpc
name: wrpc
interface: wb-16
interface: wb-16
...
...
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