Commit b70ec62f authored by Tristan Gingold's avatar Tristan Gingold

wr2rf_vme: use new phy wb interface

parent 7d90e987
......@@ -391,8 +391,8 @@ architecture rtl of wr2rf_vme is
signal phy_rx_rbclk_sampled : std_logic;
signal phy_lpc_ctrl : std_logic_vector(15 downto 0);
signal phy_lpc_stat : std_logic_vector(15 downto 0);
signal phy_mdio_out : t_wishbone_master_out;
signal phy_mdio_in : t_wishbone_master_in;
signal pps_p : std_logic;
signal pps_csync : std_logic;
......@@ -837,13 +837,17 @@ begin
inst_GTX_Link0 : entity work.wr_gtx_phy_kintex7_lp
generic map(
g_simulation => g_simulation)
port map(
port map(
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => wrcore_reset_n,
qpll_clk_i => gtx_qpll_clk,
qpll_ref_clk_i => gtx_qpll_ref_clk,
qpll_locked_i => gtx_qpll_locked,
qpll_reset_o => gtx_qpll_reset,
clk_dmtd_i => clk_dmtd_62m5,
clk_ref_i => clk_sys_62m5,
tx_clk_o => open,
tx_locked_o => open,
tx_data_i => phy_tx_data,
tx_k_i => phy_tx_k,
tx_disparity_o => phy_tx_disparity,
......@@ -855,17 +859,15 @@ begin
-- rx_bitslide_o => phy_rx_bitslide,
rx_rbclk_sampled_o => phy_rx_rbclk_sampled,
rst_i => phy_rst,
debug_i => phy_lpc_ctrl,
debug_o => phy_lpc_stat,
loopen_i => phy_loopen,
loopen_vec_i => "000",
pad_txn_o => sfp1_tx_n_o,
pad_txp_o => sfp1_tx_p_o,
pad_rxn_i => sfp1_rx_n_i,
pad_rxp_i => sfp1_rx_p_i,
tx_clk_o => open,
tx_locked_o => open,
tx_prbs_sel_i => "000",
rdy_o => phy_rdy );
rdy_o => phy_rdy,
mdio_slave_i => phy_mdio_out,
mdio_slave_o => phy_mdio_in);
inst_WR_CORE : entity work.xwr_core
generic map(
......@@ -919,8 +921,8 @@ begin
phy_rx_bitslide_i => "00000", --phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_rdy_i => phy_rdy,
phy_lpc_ctrl_o => phy_lpc_ctrl,
phy_lpc_stat_i => phy_lpc_stat,
phy_mdio_master_o => phy_mdio_out,
phy_mdio_master_i => phy_mdio_in,
phy_rx_rbclk_sampled_i => phy_rx_rbclk_sampled,
phy_loopen_o => phy_loopen,
phy_loopen_vec_o => phy_loopen_vec,
......
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