Commit b2e12226 authored by John Robert Gill's avatar John Robert Gill

added pll_sync function.

parent 870a53ae
......@@ -95,6 +95,19 @@ libwr2rf_iodelay_init(struct libwr2rf_dev *dev)
libwr2rf_write16(dev, iodelay_addr, 0);
}
void
libwr2rf_ltc6950_sync (struct libwr2rf_dev *dev)
{
unsigned addr = WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_PLL_CTRL;
unsigned val = libwr2rf_read16(dev, addr);
// provide a signal > 1ms to the ltc6950
val |= WR2RF_INIT_REGS_PLL_CTRL_SYNC;
libwr2rf_write16(dev, addr, val);
usleep(2000);
val &= ~WR2RF_INIT_REGS_PLL_CTRL_SYNC;
libwr2rf_write16(dev, addr, val);
}
void
libwr2rf_clock_init (struct libwr2rf_dev *dev)
......@@ -106,6 +119,8 @@ libwr2rf_clock_init (struct libwr2rf_dev *dev)
libwr2rf_pll_spi_init(dev);
/* 1.2 the PLL itself. */
libwr2rf_ltc6950_init (dev);
/* 1.3 sync the PLL */
libwr2rf_ltc6950_sync (dev);
/* 2. FPGA clock. */
libwr2rf_clock_select_dds (dev);
......
......@@ -30,14 +30,14 @@
{0x08, 0x01}, // R[7:0] = 1
{0x09, 0x00}, // Reset_N + N[10:8]
{0x0a, 0x0a}, // N[7:0] = 10
{0x0b, 0x04}, // disable FILTR for 100 MHz, LVCMS=1
{0x0c, 0x00}, // DEL0 = 0, No sync, No filter
{0x0b, 0xc4}, // disable FILTR for 100 MHz, LVCMS=1
{0x0c, 0x80}, // DEL0 = 0, No sync, No filter
{0x0d, 0x84}, // M0 = 4
{0x0e, 0x00}, // DEL1
{0x0e, 0x80}, // DEL1
{0x0f, 0x81}, // M1 = 1
{0x10, 0x00}, // DEL2
{0x10, 0x80}, // DEL2
{0x11, 0x88}, // M2 = 8
{0x12, 0x00}, // DEL3
{0x12, 0x80}, // DEL3
{0x13, 0x88}, // M3 = 8
{0x14, 0x00}, // DEL4
{0x14, 0x80}, // DEL4
{0x15, 0x10} // M4 = 16, RDIVOUT = 0
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