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wr2rf-vme
Commit a82fb8f0 authored by Tristan Gingold's avatar Tristan Gingold
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Update constraints

parent eb82d0d2
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Showing with 580 additions and 128 deletions
hdl/syn/wr2rf_vme/gencores_constraints.xdc
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hdl/syn/wr2rf_vme/wr2rf_vme.xdc
View file @ a82fb8f0
......@@ -1072,7 +1072,8 @@ create_clock -period 4.444 -name clk_rf2_t2 -waveform {0.000 2.222} [get_
# Transceivers need a create_clock - cannot propagate from clk_125m_gtx_p_i
create_clock -period 4.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLKFABRIC]
create_clock -period 4.000 [get_pins -hier -filter name=~*gtxe2_i*RXOUTCLK]
create_generated_clock -name gtx_txoutclk -divide_by 1 -add -source [get_ports -filter { NAME =~ "*clk_sys_62m5_p_i*" && DIRECTION == "IN" }] -master_clock clk_sys [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLK ]
#create_generated_clock -name gtx_txoutclk -divide_by 1 -add -source [get_ports -filter { NAME =~ "*clk_sys_62m5_p_i*" && DIRECTION == "IN" }] -master_clock clk_sys [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLK ]
create_clock -period 16.000 -waveform {8.5 0.5} [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLK]
create_generated_clock -name gtx_txoutclkfabric -divide_by 1 -add -source [get_ports -filter { NAME =~ "*clk_sys_62m5_p_i*" && DIRECTION == "IN" }] -master_clock clk_sys [get_pins -hier -filter name=~*gtxe2_i*TXOUTCLKFABRIC ]
# Create generated clocks on the output of the BUGMUX and then physically exclude them, See AR #59484
......@@ -1085,6 +1086,7 @@ set_clock_groups -physically_exclusive -group clk_sys_bgmux -group clk_dmtd_bgmu
# Critical paths
###################################
set_property ASYNC_REG true [get_cells -hier -filter {NAME=~*U_Sampler*gen_straight.clk_i_d*_reg}]
set_false_path -to [get_cells -hier -filter {NAME=~*U_Sampler*gen_straight.clk_i_d0_reg}]
set_max_delay -from [get_cells inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg] \
-to [get_cells inst_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_builtin.U_Sampler/gen_straight.clk_i_d1_reg] \
-datapath_only 1
......
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ a82fb8f0
......@@ -869,7 +869,7 @@ begin
--
g_board_name => "WRRF",
--g_ram_address_space_size_kb => 256,
g_phys_uart => true,
g_phys_uart => true, -- Is false OK ?
g_virtual_uart => true,
g_aux_clks => 0,
g_ep_rxbuf_size => 1024,
......
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