wr2rf_vme: use reverse dmtd

a697909b · Tristan Gingold · 2204dd56 · a224e333 · a697909b
Commit a697909b authored Sep 06, 2023 by Tristan Gingold
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Showing with 11 additions and 6 deletions

wr-cores dependencies/wr-cores +1 -1

wr2rf_vme.vhd hdl/top/wr2rf_vme/wr2rf_vme.vhd +10 -5

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--- a/wr-cores @ a224e333
+++ b/wr-cores @ a224e333
-Subproject commit 1ee142a3830995ea2e940165b3b86fb95667b019
+Subproject commit a224e333afef80ce6b7aabd906741c5de6645301
--- a/hdl/top/wr2rf_vme/wr2rf_vme.vhd
+++ b/hdl/top/wr2rf_vme/wr2rf_vme.vhd
@@ -357,6 +357,7 @@ architecture rtl of wr2rf_vme is

  signal vme_nogap          : std_logic;

+  signal clk_ref_62m5       : std_logic;
  signal clk_dmtd_62m5      : std_logic;
  signal clk_sys_62m5       : std_logic;
  signal clk_sys_62m5_in    : std_logic;
@@ -760,6 +761,8 @@ begin
            I1 => clk62m5,             -- 1-bit input: Clock input (S=1)
            S  => clk_sys_select );    -- 1-bit input: Clock select

+    clk_ref_62m5 <= clk_sys_62m5_in;
+
    inst_IBUFDS_clk_ext_10m : IBUFGDS
        generic map (
          IBUF_LOW_PWR => false
@@ -850,13 +853,14 @@ begin

    inst_GTX_Link0 : entity work.wr_gtx_phy_kintex7_lp
        generic map(
-            g_simulation => g_simulation)
+            g_simulation => g_simulation,
+            g_reverse_ddmtds => true)
      port map(
-            clk_sys_i => clk_sys_62m5,
-            rst_sys_n_i => wrcore_reset_n,
+            clk_sys_i          => clk_sys_62m5,
+            rst_sys_n_i        => wrcore_reset_n,
            clk_gtx_i          => clk_gtx_125m,
            clk_dmtd_i         => clk_dmtd_62m5,
-            clk_ref_i          => clk_sys_62m5,
+            clk_ref_i          => clk_ref_62m5,
            tx_clk_o           => open,
            tx_locked_o        => open,
            tx_data_i          => phy16_out.tx_data,
@@ -903,6 +907,7 @@ begin
            g_aux_sdb                        => c_wrc_periph3_sdb,
            g_softpll_enable_debugger        => true,
            g_softpll_use_sampled_ref_clocks => true,
+            g_softpll_reverse_dmtds          => true,
            g_diag_id                        => c_diag_id,
            g_diag_ver                       => c_diag_ver,
            g_diag_ro_size                   => c_diag_ro_size,
@@ -911,7 +916,7 @@ begin
        port map(
            clk_sys_i              => clk_sys_62m5,
            clk_dmtd_i             => clk_dmtd_62m5,
-            clk_ref_i              => clk_sys_62m5,  --clk_125m_ref,
+            clk_ref_i              => clk_ref_62m5,  --clk_125m_ref,
            clk_aux_i(0)           => clk_aux_in,
            clk_ext_i              => clk_ext_10m,
            clk_ext_mul_i          => clk_ext_mul,