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wr2rf-vme
Commit 9522d47b authored by John Gill's avatar John Gill
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Added some ctrl registers: one for wrcore_reset and the other for iodelay_reset.… 

Added some ctrl registers: one for wrcore_reset and the other for iodelay_reset. Half added rfnco register map, need missing cheby file...
parent 7f650ec9
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Showing with 158 additions and 55 deletions
hdl/rtl/registers/Manifest.py
View file @ 9522d47b
files = ['trigunit_regs.vhd',
files = ['wr2rf_rfnco_regs.vhd',
'trigunit_regs.vhd',
'vtudiag_regs.vhd',
'wr2rf_rftrigger_regs.vhd',
'wr2rf_init_rf_regs.vhd',
......
hdl/rtl/registers/gen_hdr.sh
View file @ 9522d47b
......@@ -17,5 +17,8 @@ cheby -i oc_spi16_regs.cheby --gen-c $PFX/oc_spi16_regs.h
cheby -i wr2rf_ctrl_regs.cheby --gen-c $PFX/wr2rf_ctrl_regs.h
# RFNCO
#( cd ../../../dependencies/RFNCO/MemMap/ ; cheby -i RFNCO.cheby --gen-c ) > $PFX/wr2rf_rfnco_regs.h
# Top-level memory map
cheby -i wr2rf_vme_regs.cheby --gen-c $PFX/wr2rf_vme_regs.h
hdl/rtl/registers/gen_regs.sh
View file @ 9522d47b
......@@ -8,7 +8,8 @@ cheby -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
cheby -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
# RFNCO
#( cd ../../../dependencies/RFNCO/MemMap/ ; cheby -i RFNCO.cheby --gen-hdl ) > wr2rf_rfnco_regs.vhd
# Top-level memory map
cheby -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
hdl/rtl/registers/trigunit_regs.vhd
View file @ 9522d47b
-- Do not edit. Generated on Fri Nov 13 16:48:20 2020 by jgill
-- Do not edit. Generated on Wed Nov 25 16:59:15 2020 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/registers/wr2rf_init_regs.cheby
View file @ 9522d47b
......@@ -18,6 +18,28 @@ memory-map:
description: Reset the system pll
range: 1
preset: 1
- reg:
name: wrcore_ctrl
description: Control register for wrcore
access: rw
width: 16
children:
- field:
name: reset_n
description: Reset the wrcore, active low
range: 0
preset: 0
- reg:
name: iodelay_ctrl
description: Control register for iodelayctrl
access: rw
width: 16
children:
- field:
name: reset
description: Reset the iodelay, must transition 0->1 (for > 50 ns) then 1->0
range: 0
preset: 1
- reg:
name: mmcm_shift
description: Adjust the mmcm shift for the 10Mhz external clock
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ 9522d47b
-- Do not edit. Generated on Fri Nov 13 16:48:21 2020 by jgill
-- Do not edit. Generated on Wed Nov 25 16:59:16 2020 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ 9522d47b
-- Do not edit. Generated on Fri Nov 13 16:48:20 2020 by jgill
-- Do not edit. Generated on Wed Nov 25 16:59:16 2020 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ 9522d47b
This diff is collapsed.
hdl/rtl/wr2rf_regs_core.vhd
View file @ 9522d47b
......@@ -29,7 +29,7 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity wr2rf_regs_core is
generic (
svec_mockup : boolean := false );
port (
......@@ -59,10 +59,12 @@ entity wr2rf_regs_core is
wb_dds_fpg_i : in t_wishbone_master_in;
wb_dds_fpg_o : out t_wishbone_master_out;
mmcm_locked_i : in std_logic;
clk_sel_o : out std_logic;
clk_sys_reset_o : out std_logic;
mmcm_locked_i : in std_logic;
clk_sel_o : out std_logic;
clk_sys_reset_o : out std_logic;
wrcore_reset_n_o : out std_logic;
iodelay_reset_o : out std_logic;
mmcm_shift_incdec_o : out std_logic;
mmcm_shift_en_o : out std_logic;
......@@ -115,11 +117,11 @@ entity wr2rf_regs_core is
svec_mup_rftrig_t2start_o : out std_logic;
svec_mup_fmc1_term_o : out std_logic_vector(4 downto 0);
svec_mup_fmc1_oe_n_o : out std_logic_vector(4 downto 0);
svec_mup_fmc1_oe_n_o : out std_logic_vector(4 downto 0);
svec_mup_fmc1_led_o : out std_logic_vector(1 downto 0);
svec_mup_fmc2_term_o : out std_logic_vector(4 downto 0);
svec_mup_fmc2_oe_n_o : out std_logic_vector(4 downto 0);
svec_mup_fmc2_led_o : out std_logic_vector(1 downto 0);
svec_mup_fmc2_oe_n_o : out std_logic_vector(4 downto 0);
svec_mup_fmc2_led_o : out std_logic_vector(1 downto 0);
-- RF 1
rf1_mux_sel_o : out std_logic_vector(1 downto 0);
......@@ -152,7 +154,7 @@ entity wr2rf_regs_core is
tm_linkup_i : in std_logic;
tm_time_valid_i : in std_logic;
pps_i : in std_logic := '0' );
end;
architecture arch of wr2rf_regs_core is
......@@ -174,10 +176,10 @@ architecture arch of wr2rf_regs_core is
signal fw_update_out : t_wishbone_master_out;
signal framerxtx_wb16_sys_in : t_wishbone_master_in;
signal framerxtx_wb16_sys_out : t_wishbone_master_out;
signal framerxtx_wb16_sys_out : t_wishbone_master_out;
signal framerxtx_wb16_ref_in : t_wishbone_master_in;
signal framerxtx_wb16_ref_out : t_wishbone_master_out;
signal framerxtx_wb16_ref_out : t_wishbone_master_out;
signal rf1_t1_delay_data : std_logic_vector (15 downto 0);
signal rf1_t2_delay_data : std_logic_vector (15 downto 0);
signal rf2_t1_delay_data : std_logic_vector (15 downto 0);
......@@ -186,16 +188,16 @@ architecture arch of wr2rf_regs_core is
signal rf1_t2_delay_wr : std_logic;
signal rf2_t1_delay_wr : std_logic;
signal rf2_t2_delay_wr : std_logic;
-- clk_ref based.
signal wrs_frame_valid : std_logic;
signal wrs_frame_ftw : std_logic_vector (47 downto 0);
signal wrs_frame_last_ftw : std_logic_vector (47 downto 0);
signal wrs_frame_last_ctrl : std_logic_vector (15 downto 0);
signal wrs_frame_counter : std_logic_vector (15 downto 0);
signal wrs_frame_counter : std_logic_vector (15 downto 0);
begin
inst_wr2rf_regs: entity work.wr2rf_vme_regs
port map (
rst_n_i => rst_sys_n_i,
......@@ -208,11 +210,14 @@ begin
ctrl_rf2_vtus_o => rf2_vtus_wb_o,
ctrl_reg1_o => open,
ctrl_reg2_o => open,
init_clock_status_mmcm_locked_i => mmcm_locked_i,
init_clock_ctrl_clk_sel_o => clk_sel_o,
init_clock_ctrl_mmcm_reset_o => clk_sys_reset_o,
init_wrcore_ctrl_reset_n_o => wrcore_reset_n_o,
init_iodelay_ctrl_reset_o => iodelay_reset_o,
init_mmcm_shift_incdec_o => mmcm_shift_incdec_o,
init_mmcm_shift_wr_o => mmcm_shift_en_o,
init_clock_status_shift_busy_i => mmcm_shift_busy_i,
......@@ -240,31 +245,31 @@ begin
init_nco_ctrl_reset_slip_o => open,
init_nco_ctrl_reset_fsk_o => open,
init_nco_ctrl_rate_o => open,
init_nco_update_valid_o => loc_nco_update_valid_o,
init_nco_loc_or_wrs_params_sel_o => loc_or_wrs_params_sel_o,
init_nco_update_valid_o => loc_nco_update_valid_o,
init_nco_loc_or_wrs_params_sel_o => loc_or_wrs_params_sel_o,
init_svec_mup_ctrl_gpio_sel_o => svec_mup_gpio_sel_o,
init_svec_mup_ctrl_led_sel_o => svec_mup_led_sel_o,
init_svec_mup_ctrl_bclk_rfclk_sel_o => svec_mup_bclk_rfclk_sel_o,
init_svec_mup_ctrl_ila_sel_o => svec_mup_ila_sel_o,
init_svec_mup_rftrig_t1stop_o => svec_mup_rftrig_t1stop_o,
init_svec_mup_rftrig_t1stop_o => svec_mup_rftrig_t1stop_o,
init_svec_mup_rftrig_t1start_o => svec_mup_rftrig_t1start_o,
init_svec_mup_rftrig_t2stop_o => svec_mup_rftrig_t2stop_o,
init_svec_mup_rftrig_t2stop_o => svec_mup_rftrig_t2stop_o,
init_svec_mup_rftrig_t2start_o => svec_mup_rftrig_t2start_o,
init_svec_mup_fmc1_term_o => svec_mup_fmc1_term_o,
init_svec_mup_fmc1_oe_n_o => svec_mup_fmc1_oe_n_o,
init_svec_mup_fmc1_oe_n_o => svec_mup_fmc1_oe_n_o,
init_svec_mup_fmc1_led_o => svec_mup_fmc1_led_o,
init_svec_mup_fmc2_term_o => svec_mup_fmc2_term_o,
init_svec_mup_fmc2_oe_n_o => svec_mup_fmc2_oe_n_o,
init_svec_mup_fmc2_oe_n_o => svec_mup_fmc2_oe_n_o,
init_svec_mup_fmc2_led_o => svec_mup_fmc2_led_o,
init_wrc_tai_value_i => tm_tai_i,
init_wrc_cycles_value_i => tm_cycles_i,
init_wrc_status_linkup_i => tm_linkup_i,
init_wrc_status_time_valid_i => tm_time_valid_i,
init_rxframe_ftw_value_i => wrs_frame_last_ftw,
init_rxframe_ctrl_i => wrs_frame_last_ctrl,
init_rxframe_counter_i => wrs_frame_counter,
......@@ -435,5 +440,5 @@ begin
-- fine pulse generator
-- Need to do XXX
end arch;
hdl/rtl/wr2rf_rftrigger.vhd
View file @ 9522d47b
......@@ -41,6 +41,7 @@ entity wr2rf_rftrigger is
-- Reference clock for io delays
clk_refclk_200m_i : in std_logic;
iodelay_reset_i : in std_logic;
-- Wishbone interface, uses clk_sys.
wb_i : in t_wishbone_slave_in;
......@@ -229,13 +230,11 @@ begin
O => rf_clk_bufg_o);
-- Delay control (1 per clock region)
-- XXXX FIXME reset must be deasserted/asserted for longer than 50 ns -
-- poweron reset wont work!!! There's no 0->1 transition just 1->0
rf_IDELAYCTRL : IDELAYCTRL
port map (
RDY => rf_idelay_rdy, -- 1-bit output: Ready output
REFCLK => clk_refclk_200m_i, -- 1-bit input: Reference clock input
RST => rst_sys_i); -- 1-bit input: Active high reset input
RDY => rf_idelay_rdy, -- 1-bit output: Ready output
REFCLK => clk_refclk_200m_i, -- 1-bit input: Reference clock input
RST => iodelay_reset_i ); -- 1-bit input: Active high reset input
-- Diag for rf_clk.
inst_rf_diag: entity work.vtu_diag
......
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 9522d47b
......@@ -407,6 +407,8 @@ architecture rtl of wr2rf_vme is
signal rf2_sync : std_logic;
signal mmcm_locked : std_logic;
signal wrcore_reset_n : std_logic;
signal iodelay_reset : std_logic;
signal rf1_vtus_wb_in : t_wishbone_master_in;
signal rf1_vtus_wb_out : t_wishbone_master_out;
......@@ -677,7 +679,7 @@ begin
clk_ext_mul_locked_i => '1',
clk_ext_i => clk_ext_10m_in,
pps_ext_i => pps_i,
rst_n_i => rst_sys_n,
rst_n_i => wrcore_reset_n,
dac_hpll_load_p1_o => dac_hpll_load_p1_o,
dac_hpll_data_o => dac_hpll_data_o,
dac_dpll_load_p1_o => dac_dpll_load_p1_o,
......@@ -1055,6 +1057,7 @@ begin
rst_sys_n_i => rst_sys_n,
rst_sys_i => rst_sys,
clk_refclk_200m_i => clk200m,
iodelay_reset_i => iodelay_reset,
wb_i => rf1_vtus_wb_out,
wb_o => rf1_vtus_wb_in,
......@@ -1088,6 +1091,7 @@ begin
rst_sys_n_i => rst_sys_n,
rst_sys_i => rst_sys,
clk_refclk_200m_i => clk200m,
iodelay_reset_i => iodelay_reset,
wb_i => rf2_vtus_wb_out,
wb_o => rf2_vtus_wb_in,
......@@ -1160,6 +1164,8 @@ begin
mmcm_locked_i => mmcm_locked,
clk_sel_o => clk_sys_select,
clk_sys_reset_o => clk_sys_reset,
wrcore_reset_n_o => wrcore_reset_n,
iodelay_reset_o => iodelay_reset,
mmcm_shift_incdec_o => mmcm_shift_incdec,
mmcm_shift_en_o => mmcm_shift_en,
......
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