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Commit 90d378bd authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: improve style.

parent 92676136
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Showing with 55 additions and 90 deletions
dependencies/vtu/rtl/vtuCore.vhd
View file @ 90d378bd
......@@ -1400,48 +1400,38 @@ architecture vtuCore of vtuCore is
signal visual_B_SwitchHTFF_Q : std_logic;
begin
B_DataShifterB: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '1'
)
port map (
CoarseZero => BCoarseZero,
g_DisableDoubleSync => '1')
port map (CoarseZero => BCoarseZero,
DataOut => DataOut_1(7 downto 0),
OutputEnabled => OE_1,
Clk => Clk,
Delay => bValue(63 downto 0),
DataIn => DataIn(7 downto 0),
Enabled => Shifter1Ena,
SyncPulse => SyncPulse_i
);
SyncPulse => SyncPulse_i);
B_DataShifterHT: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '0'
)
port map (
CoarseZero => HTCoarseZero,
g_DisableDoubleSync => '0')
port map (CoarseZero => HTCoarseZero,
DataOut => DataOut_2(7 downto 0),
OutputEnabled => OE_2,
Clk => Clk,
Delay => htValue_effective(63 downto 0),
DataIn => DataIn_2(7 downto 0),
Enabled => Shifter2Ena,
SyncPulse => open
);
SyncPulse => open);
B_LimSubtr: entity work.LimSubtrN
port map (
A => wValue(63 downto 0),
port map (A => wValue(63 downto 0),
B => COne(63 downto 0),
lim => open,
O => wValue_effective(63 downto 0)
);
O => wValue_effective(63 downto 0));
B_vtuSeq: entity work.vtuSeq
port map (
Clk => Clk,
port map (Clk => Clk,
Rst => Rst,
Start => Start_seq,
Stop => Stop_seq,
......@@ -1454,72 +1444,57 @@ begin
wValueOne => wValueOne_seq,
WindowDone => WindowDone_seq,
CounterRst => counterReset,
Run => Run_seq
);
Run => Run_seq);
B_DataShifterHT_SyncLess: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '0'
)
port map (
CoarseZero => open,
g_DisableDoubleSync => '0')
port map (CoarseZero => open,
DataOut => DataOutHTSyncLess(7 downto 0),
OutputEnabled => OE_SyncLess,
Clk => Clk,
Delay => htValue_effective(63 downto 0),
DataIn => DataInHTSyncLess(7 downto 0),
Enabled => SyncLessEna,
SyncPulse => open
);
SyncPulse => open);
B_RSFFSyncLessMux: entity work.RSFF
port map (
Clk => Clk,
port map (Clk => Clk,
Set => StartSyncLess,
Clr => SetStartData,
Rst => Rst,
Q => SetStartData
);
Q => SetStartData);
B_RSFFRunSyncLess: entity work.RSFF
port map (
Clk => Clk,
port map (Clk => Clk,
Set => StartSyncLess,
Clr => SyncLessDisabled,
Rst => Rst,
Q => RunSyncLess
);
Q => RunSyncLess);
B_PlayMemRunningFF: entity work.RSFF
port map (
Clk => Clk,
port map (Clk => Clk,
Set => StartPlayMem,
Clr => StopPlayMem,
Rst => Rst,
Q => RunPlayMem_i
);
Q => RunPlayMem_i);
B_FirstSyncFF: entity work.RSFF
port map (
Clk => Clk,
port map (Clk => Clk,
Set => RunPlayAndSyncPulse,
Clr => StopPlayMem,
Rst => Rst,
Q => FirstSyncArrived
);
Q => FirstSyncArrived);
B_PlayingMemFF: entity work.RSFF
port map (
Clk => Clk,
port map (Clk => Clk,
Set => SetPlayingMem,
Clr => StopPlayMem,
Rst => Rst,
Q => PlayingMem_i
);
Q => PlayingMem_i);
B_PlayMemLogic: entity work.PlayMemLogic
port map (
Clk => Clk,
port map (Clk => Clk,
RunPlayMem => RunPlayMem,
FirstOutput => FirstOutput,
PlayingMem => PlayingMem,
......@@ -1530,23 +1505,19 @@ begin
FirstBit => FirstBit(2 downto 0),
LastBit => Mem_LastBit(2 downto 0),
Mem_Addr => Mem_Addr_i(14 downto 0),
DataOut => DataOutPlayMem(7 downto 0)
);
DataOut => DataOutPlayMem(7 downto 0));
B_ModeSelDecoder: entity work.ModeSelDecoder
port map (
Mode => Mode(2 downto 0),
port map (Mode => Mode(2 downto 0),
SinglePulseMode => SinglePulseMode,
InfiniteWindowMode => InfiniteWindowMode,
WindowedOperationMode => WindowedOperationMode,
SyncLessOperationMode => SyncLessOperationMode,
LowFreqGenerationMode => LowFreqGenerationMode,
PlayMemoryMode => PlayMemoryMode
);
PlayMemoryMode => PlayMemoryMode);
B_WrongValuesLogic: entity work.WrongValuesLogic
port map (
wrongB => wrongB_s,
port map (wrongB => wrongB_s,
wrongHT => wrongHT_s,
wrongW => wrongW_s,
BCoarseZero => BCoarseZero,
......@@ -1555,30 +1526,27 @@ begin
wValueZero => wValueZero,
Mode => Mode(2 downto 0),
Clk => Clk,
Rst => Rst
);
Rst => Rst);
B_LimAdder: entity work.LimAdderN
port map (
A => htValue(63 downto 0),
port map (A => htValue(63 downto 0),
B => COne(63 downto 0),
lim => open,
O => htValuePlusOne(63 downto 0)
);
O => htValuePlusOne(63 downto 0));
wrongValue <= wrongB_s or wrongHT_s or wrongW_s;
wrongValue <= wrongB_s or wrongHT_s or wrongW_s;
Stop_seq <= Stop or wrongValue;
Stop_seq <= Stop or wrongValue;
process (Start, SyncPulse_i, UseSyncAsStart)
begin
case UseSyncAsStart is
when '0' =>
Start_i <= Start;
when others =>
Start_i <= SyncPulse_i;
end case;
end process;
begin
case UseSyncAsStart is
when '0' =>
Start_i <= Start;
when others =>
Start_i <= SyncPulse_i;
end case;
end process;
wrongB <= wrongB_s;
......@@ -1587,14 +1555,14 @@ begin
wrongW <= wrongW_s;
process (Start_i, NoStart, DisconnectStart)
begin
begin
case DisconnectStart is
when '0' =>
Start_seq <= Start_i;
when others =>
Start_seq <= NoStart;
end case;
end process;
end process;
NoStart <= '0';
......@@ -1608,7 +1576,7 @@ begin
SyncPulse <= SyncPulse_i;
process (htValue , htValuePlusOne , SwitchHTeffective)
begin
begin
case SwitchHTeffective is
when '0' =>
htValue_effective(63 downto 0) <= htValue(63 downto 0);
......@@ -1622,15 +1590,13 @@ begin
process (Clk , Run_n)
begin
if (Run_n = '1') then
if Run_n = '1' then
visual_B_SwitchHTFF_Q <= '0';
elsif (Clk'event and Clk = '1') then
if (HTSwitchEna = '1') then
elsif Clk'event and Clk = '1' then
if HTSwitchEna = '1' then
visual_B_SwitchHTFF_Q <= (SwitchHTeffective_n);
end if;
end if;
end if;
end process;
COne(63 downto 0) <= (0=> '1', others => '0');
......@@ -1665,8 +1631,7 @@ begin
end case;
end process;
PulseCount(63 downto 0) <= (visual_B_PulseCounter_cur_state);
PulseCount(63 downto 0) <= visual_B_PulseCounter_cur_state;
visual_B_PulseCounter_en_state <= visual_B_PulseCounter_next_count
when counterEnable = '1'
......@@ -1676,8 +1641,8 @@ begin
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (counterReset = '1') then
if Clk'event and Clk = '1' then
if counterReset = '1' then
visual_B_PulseCounter_cur_state <= (others => '0');
else
visual_B_PulseCounter_cur_state <= visual_B_PulseCounter_next_state;
......@@ -1706,7 +1671,7 @@ begin
end if;
end process;
process (wValue_effective , CZero)
process (wValue_effective, CZero)
begin
if wValue_effective(63 downto 0) = CZero(63 downto 0) then
wValueOne <= '1';
......@@ -1715,7 +1680,7 @@ begin
end if;
end process;
process (CZero , wValue)
process (CZero, wValue)
begin
if CZero(63 downto 0) = wValue(63 downto 0) then
wValueZero <= '1';
......@@ -1726,9 +1691,9 @@ begin
CZero(63 downto 0) <= (others => '0');
WindowDone_seq <= ( WindowDone) and (not InfiniteWindow);
WindowDone_seq <= WindowDone and (not InfiniteWindow);
counterEnable <= (( OE_1) or ( OE_2)) and (( Run_seq));
counterEnable <= (OE_1 or OE_2) and Run_seq;
wValueOne_seq <= (wValueOne or SinglePulseMode) and (not InfiniteWindow);
......
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