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wr2rf-vme
Commit 8a28d599 authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore.vhd: use direct instantiations.

parent a578965d
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Showing with 15 additions and 117 deletions
dependencies/vtu/rtl/vtuCore.vhd
View file @ 8a28d599
......@@ -1309,8 +1309,6 @@ entity vtuCore is
Run : out std_logic;
Clk : in std_logic
);
end vtuCore;
......@@ -1405,107 +1403,7 @@ architecture vtuCore of vtuCore is
signal RunPlayAndSyncPulse : std_logic;
signal RunPlayMem_i : std_logic;
signal ReadDataZero : std_logic;
component vtuDataShifter
generic (
N : INTEGER := 16;
g_DisableDoubleSync : std_logic := '1'
);
port (
CoarseZero : out std_logic;
DataOut : out std_logic_vector(7 downto 0 );
OutputEnabled : out std_logic;
Clk : in std_logic;
Delay : in std_logic_vector(N - 1 downto 0 );
DataIn : in std_logic_vector(7 downto 0 );
Enabled : in std_logic;
SyncPulse : out std_logic
);
end component;
component LimSubtrN
port (
A : in std_logic_vector;
B : in std_logic_vector;
lim : out std_logic;
O : out std_logic_vector
);
end component;
component vtuSeq
port (
Clk : in std_logic;
Rst : in std_logic;
Start : in std_logic;
Stop : in std_logic;
SyncPulse : in std_logic;
OutputEnable1 : in std_logic;
OutputEnable2 : in std_logic;
Shifter1Ena : out std_logic;
Shifter2Ena : out std_logic;
SwitchtoHT : out std_logic;
wValueOne : in std_logic;
WindowDone : in std_logic;
RestartEnable : in std_logic;
CounterRst : out std_logic;
Run : out std_logic
);
end component;
component RSFF
port (
Clk : in std_logic;
Set : in std_logic;
Clr : in std_logic;
Rst : in std_logic := '0';
Q : out std_logic
);
end component;
component PlayMemLogic
port (
Clk : in std_logic;
RunPlayMem : in std_logic;
FirstOutput : in std_logic;
PlayingMem : in std_logic;
LastElem : in std_logic_vector;
RdData : in std_logic_vector(7 downto 0 );
RdDataPrev : in std_logic_vector(7 downto 0 );
RdDataZero : in std_logic_vector(7 downto 0 );
FirstBit : in std_logic_vector(2 downto 0 );
LastBit : in std_logic_vector(2 downto 0 );
Mem_Addr : out std_logic_vector;
DataOut : out std_logic_vector(7 downto 0 )
);
end component;
component ModeSelDecoder
port (
Mode : in std_logic_vector(2 downto 0 );
SinglePulseMode : out std_logic;
InfiniteWindowMode : out std_logic;
WindowedOperationMode : out std_logic;
SyncLessOperationMode : out std_logic;
LowFreqGenerationMode : out std_logic;
PlayMemoryMode : out std_logic
);
end component;
component WrongValuesLogic
port (
wrongB : out std_logic;
wrongHT : out std_logic;
wrongW : out std_logic;
BCoarseZero : in std_logic;
HTCoarseZero : in std_logic;
wValueOne : in std_logic;
wValueZero : in std_logic;
Mode : in std_logic_vector(2 downto 0 );
Clk : in std_logic;
Rst : in std_logic
);
end component;
component LimAdderN
port (
A : in std_logic_vector;
B : in std_logic_vector;
lim : out std_logic;
O : out std_logic_vector
);
end component;
signal visual_B_PulseCounter_cur_state : std_logic_vector(64 - 1 downto 0 );
signal visual_B_PulseCounter_next_state : std_logic_vector(64 - 1 downto 0 );
signal visual_B_PulseCounter_next_count : std_logic_vector(64 - 1 downto 0 );
......@@ -1515,7 +1413,7 @@ architecture vtuCore of vtuCore is
begin
B_DataShifterB: vtuDataShifter
B_DataShifterB: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '1'
)
......@@ -1530,7 +1428,7 @@ begin
SyncPulse => SyncPulse_i
);
B_DataShifterHT: vtuDataShifter
B_DataShifterHT: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '0'
)
......@@ -1545,7 +1443,7 @@ begin
SyncPulse => open
);
B_LimSubtr: LimSubtrN
B_LimSubtr: entity work.LimSubtrN
port map (
A => wValue(63 downto 0),
B => COne(63 downto 0),
......@@ -1553,7 +1451,7 @@ begin
O => wValue_effective(63 downto 0)
);
B_vtuSeq: vtuSeq
B_vtuSeq: entity work.vtuSeq
port map (
Clk => Clk,
Rst => Rst,
......@@ -1572,7 +1470,7 @@ begin
Run => Run_seq
);
B_DataShifterHT_SyncLess: vtuDataShifter
B_DataShifterHT_SyncLess: entity work.vtuDataShifter
generic map (N => 64,
g_DisableDoubleSync => '0'
)
......@@ -1587,7 +1485,7 @@ begin
SyncPulse => open
);
B_RSFFSyncLessMux: RSFF
B_RSFFSyncLessMux: entity work.RSFF
port map (
Clk => Clk,
Set => StartSyncLess,
......@@ -1596,7 +1494,7 @@ begin
Q => SetStartData
);
B_RSFFRunSyncLess: RSFF
B_RSFFRunSyncLess: entity work.RSFF
port map (
Clk => Clk,
Set => StartSyncLess,
......@@ -1605,7 +1503,7 @@ begin
Q => RunSyncLess
);
B_PlayMemRunningFF: RSFF
B_PlayMemRunningFF: entity work.RSFF
port map (
Clk => Clk,
Set => StartPlayMem,
......@@ -1614,7 +1512,7 @@ begin
Q => RunPlayMem_i
);
B_FirstSyncFF: RSFF
B_FirstSyncFF: entity work.RSFF
port map (
Clk => Clk,
Set => RunPlayAndSyncPulse,
......@@ -1623,7 +1521,7 @@ begin
Q => FirstSyncArrived
);
B_PlayingMemFF: RSFF
B_PlayingMemFF: entity work.RSFF
port map (
Clk => Clk,
Set => SetPlayingMem,
......@@ -1632,7 +1530,7 @@ begin
Q => PlayingMem_i
);
B_PlayMemLogic: PlayMemLogic
B_PlayMemLogic: entity work.PlayMemLogic
port map (
Clk => Clk,
RunPlayMem => RunPlayMem,
......@@ -1648,7 +1546,7 @@ begin
DataOut => DataOutPlayMem(7 downto 0)
);
B_ModeSelDecoder: ModeSelDecoder
B_ModeSelDecoder: entity work.ModeSelDecoder
port map (
Mode => Mode(2 downto 0),
SinglePulseMode => SinglePulseMode,
......@@ -1659,7 +1557,7 @@ begin
PlayMemoryMode => PlayMemoryMode
);
B_WrongValuesLogic: WrongValuesLogic
B_WrongValuesLogic: entity work.WrongValuesLogic
port map (
wrongB => wrongB_s,
wrongHT => wrongHT_s,
......@@ -1673,7 +1571,7 @@ begin
Rst => Rst
);
B_LimAdder: LimAdderN
B_LimAdder: entity work.LimAdderN
port map (
A => htValue(63 downto 0),
B => COne(63 downto 0),
......
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