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wr2rf-vme
Commit 7ab6dc40 authored by John Robert Gill's avatar John Robert Gill
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parents d35046d2 2dddacb8
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hdl/rtl/registers/trigunit_regs.vhd
View file @ 7ab6dc40
-- Do not edit. Generated on Mon Apr 12 10:57:22 2021 by jgill
-- Do not edit. Generated on Fri Apr 16 10:16:55 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/registers/wr2rf_init_rf_ch_regs.cheby
View file @ 7ab6dc40
......@@ -43,6 +43,16 @@ memory-map:
name: odelay
range: 15-11
preset: 0
- reg:
name: rst_cdelay
description: How many sys-cycles is the rst applied less than cdelay
access: rw
width: 16
children:
- field:
name: offset
range: 6-0
preset: 8
- repeat:
name: ch
count: 2
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ 7ab6dc40
This diff is collapsed.
hdl/rtl/registers/wr2rf_rfnco_regs.vhd
View file @ 7ab6dc40
-- Do not edit. Generated on Mon Apr 12 10:57:25 2021 by jgill
-- Do not edit. Generated on Fri Apr 16 10:16:57 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i RFNCO.cheby --gen-hdl
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ 7ab6dc40
-- Do not edit. Generated on Mon Apr 12 10:57:24 2021 by jgill
-- Do not edit. Generated on Fri Apr 16 10:16:56 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ 7ab6dc40
-- Do not edit. Generated on Mon Apr 12 10:57:26 2021 by jgill
-- Do not edit. Generated on Fri Apr 16 10:16:58 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......@@ -2048,7 +2048,7 @@ begin
init_rf_o.stb <= init_rf_tr;
init_rf_wack <= init_rf_i.ack and init_rf_wt;
init_rf_rack <= init_rf_i.ack and init_rf_rt;
init_rf_o.adr <= ((26 downto 0 => '0') & adr_int(4 downto 1)) & (0 downto 0 => '0');
init_rf_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 1)) & (0 downto 0 => '0');
init_rf_o.sel(1 downto 0) <= wr_sel_d0;
init_rf_o.we <= init_rf_wt;
init_rf_o.dat(15 downto 0) <= wr_dat_d0;
......
hdl/rtl/vtu/vtuCore.vhd
View file @ 7ab6dc40
......@@ -806,6 +806,9 @@ begin
wrongHT <= HTCoarseZero;
when C_Code_ctuAsVtu_control2_mode_playMemory =>
wrongB <= BCoarseZero;
when C_Code_ctuAsVtu_control2_mode_highFreqGeneration =>
wrongB <= BCoarseZero;
wrongHT <= HTCoarseZero;
when others =>
-- Unknown mode
wrongB <= '1';
......
hdl/rtl/vtu_blk.vhd
View file @ 7ab6dc40
......@@ -33,7 +33,9 @@ use work.wishbone_pkg.all;
entity vtu_blk is
generic (
trigger_unit_t1 : boolean := true );
trigger_unit_t1 : boolean := true;
g_output_stage : string := "serdes"; -- "ddr"
g_hc_string : string := "DDR" );
port (
-- System clock (125Mhz or 62.5Mhz)
clk_sys_i : in std_logic;
......@@ -41,20 +43,22 @@ entity vtu_blk is
rst_sys_i : in std_logic;
-- RF reset due to nco_reset
rst_rf_n_i : in std_logic;
rst_serdes_i : in std_logic;
-- Wishbone interface, uses clk_sys.
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- RF clock (~200Mhz) for serdes
clk_rf_io_i : in std_logic;
clk_rf_io_i : in std_logic;
-- RF clock (~200Mhz) for fabric
clk_rf_i : in std_logic;
clk_rf_i : in std_logic;
-- RF clock / 8 (for vtu)
clk_vtu_i : in std_logic;
clk_vtu_i : in std_logic;
clk_vtu_x2_i : in std_logic;
-- Sync input for the trigger unit
sync_i : in std_logic;
sync_x8_fb_i : in std_logic_vector(7 downto 0);
......@@ -176,6 +180,19 @@ architecture rtl of vtu_blk is
signal clk_rf_io_n : std_logic;
signal sync_data_out_clean : std_logic_vector(7 downto 0);
signal sync_data_out_clean_r : std_logic_vector(7 downto 0);
signal sync_data_x16_nohc : std_logic_vector(15 downto 0);
signal sync_data_x16_hc : std_logic_vector(15 downto 0);
signal sync_data_x16 : std_logic_vector(15 downto 0);
signal vtu_clk_r : std_logic;
signal sync_data_oserdes : std_logic_vector(7 downto 0);
signal clk_vtu_hold_delay_n : std_logic;
signal clk_vtu_hold_delay : std_logic;
attribute dont_touch : string;
attribute dont_touch of clk_vtu_hold_delay_n : signal is "true";
attribute dont_touch of clk_vtu_hold_delay : signal is "true";
-- IOB the trigger unit flip-flop reset driver.
signal trig_rst_r : std_logic;
......@@ -531,7 +548,16 @@ begin
--ila_dbg_o(10) <= sys_trig_odelay_hc;
--ila_dbg_o(15 downto 11) <= (others => '0');
ila_dbg_o <= dbg;
ila_dbg_o(7 downto 0) <= sync_data_in;
ila_dbg_o(8) <= rst_serdes_i;
ila_dbg_o(9) <= '0';
ila_dbg_o(10) <= clk_vtu_i;
ila_dbg_o(11) <= clk_vtu_x2_i;
ila_dbg_o(12) <= rst_rf_n_i;
ila_dbg_o(15 downto 13) <= (others => '0');
--ila_dbg_o <= dbg;
g_t1_true : if trigger_unit_t1 generate
......@@ -581,7 +607,7 @@ begin
DDLY => '0', -- 1-bit input: Serial data from IDELAYE2
OFB => '0', -- 1-bit input: Data feedback from OSERDESE2
OCLKB => '0', -- 1-bit input: High speed negative edge output clock
RST => rst_vtu, -- 1-bit input: Active high asynchronous reset
RST => rst_serdes_i, --rst_vtu, -- 1-bit input: Active high asynchronous reset
SHIFTIN1 => '0', -- SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
SHIFTIN2 => '0' );
end generate;
......@@ -641,17 +667,111 @@ begin
d_i => sys_trig_delay_hc,
q_o => trig_delay_hc );
inst_trig_x8oddr : entity work.x8oddr
port map (
clk_rf_io_i => clk_rf_io_i,
clk_rf_i => clk_rf_i,
rst_rf_n_i => rst_rf_n_i,
clk_vtu_i => clk_vtu_i,
rst_vtu_n_i => rst_vtu_n,
data_out_i => sync_data_out,
hc_delay_i => trig_delay_hc,
ddr_data_o => trig_out,
dbg_o => dbg );
g_ddr : if g_output_stage = "ddr" generate
inst_trig_x8oddr : entity work.x8oddr
port map (
clk_rf_io_i => clk_rf_io_i,
clk_rf_i => clk_rf_i,
rst_rf_n_i => rst_rf_n_i,
clk_vtu_i => clk_vtu_i,
rst_vtu_n_i => rst_vtu_n,
data_out_i => sync_data_out,
hc_delay_i => trig_delay_hc,
ddr_data_o => trig_out,
dbg_o => dbg );
end generate;
g_serdes : if g_output_stage = "serdes" generate
begin
sync_data_out_clean <= (others => '0') when rst_rf_n_i = '0' else sync_data_out;
sync_data_x16_nohc <= sync_data_out_clean(7) & sync_data_out_clean(7) &
sync_data_out_clean(6) & sync_data_out_clean(6) &
sync_data_out_clean(5) & sync_data_out_clean(5) &
sync_data_out_clean(4) & sync_data_out_clean(4) &
sync_data_out_clean(3) & sync_data_out_clean(3) &
sync_data_out_clean(2) & sync_data_out_clean(2) &
sync_data_out_clean(1) & sync_data_out_clean(1) &
sync_data_out_clean(0) & sync_data_out_clean(0);
sync_data_x16_hc <= sync_data_out_clean_r(0) & sync_data_out_clean(7) &
sync_data_out_clean(7) & sync_data_out_clean(6) &
sync_data_out_clean(6) & sync_data_out_clean(5) &
sync_data_out_clean(5) & sync_data_out_clean(4) &
sync_data_out_clean(4) & sync_data_out_clean(3) &
sync_data_out_clean(3) & sync_data_out_clean(2) &
sync_data_out_clean(2) & sync_data_out_clean(1) &
sync_data_out_clean(1) & sync_data_out_clean(0);
sync_data_x16 <= sync_data_x16_nohc when trig_delay_hc = '0' else sync_data_x16_hc;
clk_vtu_hold_delay_n <= (not clk_vtu_i);
clk_vtu_hold_delay <= (not clk_vtu_hold_delay_n);
process (clk_vtu_i) is
begin
if rising_edge(clk_vtu_i) then
sync_data_out_clean_r <= sync_data_out_clean;
end if;
end process;
process (clk_vtu_x2_i) is
begin
if rising_edge(clk_vtu_x2_i) then
vtu_clk_r <= clk_vtu_hold_delay;
end if;
end process;
g_hc_true : if g_hc_string = "DDR" generate
begin
sync_data_oserdes <= sync_data_x16(15 downto 8) when vtu_clk_r = '0' else sync_data_x16(7 downto 0);
end generate;
g_hc_false : if g_hc_string = "SDR" generate
begin
sync_data_oserdes <= sync_data_out_clean;
end generate;
inst_trig_OSERDESE2 : OSERDESE2
generic map (
DATA_RATE_OQ => g_hc_string, -- DDR, SDR
DATA_RATE_TQ => "SDR", -- DDR, BUF, SDR
DATA_WIDTH => 8, -- Parallel data width (2-8,10,14)
INIT_OQ => '0', -- Initial value of OQ output (1'b0,1'b1)
INIT_TQ => '0', -- Initial value of TQ output (1'b0,1'b1)
SERDES_MODE => "MASTER", -- MASTER, SLAVE
SRVAL_OQ => '0', -- OQ output value when SR is used (1'b0,1'b1)
SRVAL_TQ => '0', -- TQ output value when SR is used (1'b0,1'b1)
TBYTE_CTL => "FALSE", -- Enable tristate byte operation (FALSE, TRUE)
TBYTE_SRC => "FALSE", -- Tristate byte source (FALSE, TRUE)
TRISTATE_WIDTH => 1 -- 3-state converter width (1,4)
)
port map (
OFB => trig_out, -- 1-bit output: Feedback path for data
OQ => open, -- 1-bit output: Data path output
SHIFTOUT1 => open, -- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT2 => open,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => clk_rf_io_i, -- 1-bit input: High speed clock
CLKDIV => clk_vtu_x2_i, -- 1-bit input: Divided clock
D1 => sync_data_oserdes(7), -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D2 => sync_data_oserdes(6),
D3 => sync_data_oserdes(5),
D4 => sync_data_oserdes(4),
D5 => sync_data_oserdes(3),
D6 => sync_data_oserdes(2),
D7 => sync_data_oserdes(1),
D8 => sync_data_oserdes(0),
OCE => '1', -- 1-bit input: Output data clock enable
RST => rst_serdes_i, -- 1-bit input: Reset
SHIFTIN1 => '0', -- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN2 => '0',
T1 => '0', -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' -- 1-bit input: 3-state clock enable
);
end generate;
g_odelay_out : for i in 0 to 4 generate
begin
......
hdl/rtl/wr2rf_lemo.vhd
View file @ 7ab6dc40
......@@ -228,6 +228,7 @@ begin
process (clk_sys_i) is
begin
if rising_edge(clk_sys_i) then
-- to support using the same lemo for stop + start, we delay the start wrt stop
rf1_t1_start_r <= rf1_t1_start & rf1_t1_start_r(3 downto 1);
rf1_t2_start_r <= rf1_t2_start & rf1_t2_start_r(3 downto 1);
rf2_t1_start_r <= rf2_t1_start & rf2_t1_start_r(3 downto 1);
......
hdl/rtl/wr2rf_regs_core.vhd
View file @ 7ab6dc40
......@@ -210,6 +210,7 @@ entity wr2rf_regs_core is
rf1_t2_rst_o : out std_logic;
rf1_t2_delay_latch_o : out std_logic;
rf1_start_lpbk_o : out std_logic;
rf1_rst_cdelay_offset_o : out std_logic_vector(6 downto 0);
rf1_t1_sync_cdelay_o : out std_logic_vector(6 downto 0);
rf1_t1_sync_fdelay_o : out std_logic_vector(3 downto 0);
rf1_t1_sync_odelay_o : out std_logic_vector(4 downto 0);
......@@ -228,7 +229,8 @@ entity wr2rf_regs_core is
rf2_t2_mux_sel_o : out std_logic;
rf2_t2_rst_o : out std_logic;
rf2_t2_delay_latch_o : out std_logic;
rf2_start_lpbk_o : out std_logic;
rf2_start_lpbk_o : out std_logic;
rf2_rst_cdelay_offset_o : out std_logic_vector(6 downto 0);
rf2_t1_sync_cdelay_o : out std_logic_vector(6 downto 0);
rf2_t1_sync_fdelay_o : out std_logic_vector(3 downto 0);
rf2_t1_sync_odelay_o : out std_logic_vector(4 downto 0);
......@@ -336,8 +338,8 @@ begin
init_hwinfo_ident_jtagRemoteDisable_i => '1',
init_hwinfo_ident_extendedID_i => "0000000",
init_hwinfo_ident_cardID_i => x"56",
init_hwinfo_firmwareVersion_i => x"0000_10_00",
init_hwinfo_memMapVersion_i => x"0000_10_00",
init_hwinfo_firmwareVersion_i => x"0000_11_00",
init_hwinfo_memMapVersion_i => x"0000_11_00",
init_hwinfo_echo_echo_o => open,
init_fw_update_i => wb_fw_update_in,
......@@ -590,6 +592,7 @@ begin
rf1_common_mux_sel_o => rf1_mux_sel_o,
rf1_common_iqdac_reset_o => rf1_iqdac_reset_o,
rf1_common_start_lpbk_o => rf1_start_lpbk_o,
rf1_rst_cdelay_offset_o => rf1_rst_cdelay_offset_o,
rf1_t1_sync_progdelay_cdelay_o => rf1_t1_sync_cdelay_o,
rf1_t1_sync_progdelay_fdelay_o => rf1_t1_sync_fdelay_o,
rf1_t1_sync_progdelay_odelay_o => rf1_t1_sync_odelay_o,
......@@ -605,6 +608,7 @@ begin
rf2_common_mux_sel_o => rf2_mux_sel_o,
rf2_common_iqdac_reset_o => rf2_iqdac_reset_o,
rf2_common_start_lpbk_o => rf2_start_lpbk_o,
rf2_rst_cdelay_offset_o => rf2_rst_cdelay_offset_o,
rf2_t1_sync_progdelay_cdelay_o => rf2_t1_sync_cdelay_o,
rf2_t1_sync_progdelay_fdelay_o => rf2_t1_sync_fdelay_o,
rf2_t1_sync_progdelay_odelay_o => rf2_t1_sync_odelay_o,
......
hdl/rtl/wr2rf_rftrigger.vhd
View file @ 7ab6dc40
......@@ -62,7 +62,8 @@ entity wr2rf_rftrigger is
rf_t1_sync_cdelay_i : in std_logic_vector(6 downto 0);
rf_t1_sync_fdelay_i : in std_logic_vector(3 downto 0);
rf_t1_sync_odelay_i : in std_logic_vector(4 downto 0);
rf_nco_reset_cdelayed_o : out std_logic;
rf_rst_cdelay_offset_i : in std_logic_vector(6 downto 0);
rf_nco_reset_cdelayed_o : out std_logic;
rf_rst_o : out std_logic;
rf_t1_clk_p_i : in std_logic;
......@@ -105,9 +106,9 @@ architecture rtl of wr2rf_rftrigger is
signal rf_clk_in : std_logic;
signal clk_rf : std_logic;
signal rf_clk_io : std_logic;
signal clk_vtu : std_logic;
signal rf_clk_io : std_logic;
signal clk_vtu : std_logic;
signal clk_vtu_x2 : std_logic;
signal rf_idelay_rdy : std_logic;
signal rf_t1_out : std_logic;
......@@ -142,6 +143,7 @@ architecture rtl of wr2rf_rftrigger is
signal sync_serdes_tristate : std_logic;
signal async_cdc_rst_rf_n_r : std_logic;
signal cdc_rst_rf_n_r : std_logic;
signal cdc_rst_rf_n_h : std_logic;
signal t1_rst_rf_n_r : std_logic;
signal t2_rst_rf_n_r : std_logic;
......@@ -164,10 +166,20 @@ architecture rtl of wr2rf_rftrigger is
signal rf_sync_fb : std_logic;
signal rf_t1_sync_x8_fb : std_logic_vector(7 downto 0);
signal bufr_clr : std_logic;
signal clk_rf_special : std_logic;
signal t1_rst_rf_n_h : std_logic;
signal t2_rst_rf_n_h : std_logic;
signal t1_rst_vtu_pulse : std_logic;
signal t2_rst_vtu_pulse : std_logic;
signal t1_rst_vtu_pulse_r : std_logic;
signal t2_rst_vtu_pulse_r : std_logic;
attribute async_reg : string;
attribute async_reg of async_cdc_rst_rf_n_r : signal is "true";
attribute async_reg of cdc_rst_rf_n_r : signal is "true";
attribute async_reg of cdc_rst_rf_n_h : signal is "true";
attribute max_fanout : integer;
attribute max_fanout of t1_rst_rf_n_r : signal is 8;
......@@ -195,44 +207,75 @@ begin
I => rf_clk_in );
-- Sync nco_reset into the RF clk domain
process (rf_clk_in, rst_rf_r) is
process (clk_rf_special, rst_rf_r) is
begin
if rst_rf_r = '1' then
async_cdc_rst_rf_n_r <= '0';
cdc_rst_rf_n_r <= '0';
elsif rising_edge (rf_clk_in) then
cdc_rst_rf_n_h <= '0';
elsif rising_edge (clk_rf_special) then
async_cdc_rst_rf_n_r <= '1';
cdc_rst_rf_n_r <= async_cdc_rst_rf_n_r;
cdc_rst_rf_n_h <= cdc_rst_rf_n_r;
end if;
end process;
process (clk_rf) is
bufr_clr <= '1' when cdc_rst_rf_n_h = '0' and cdc_rst_rf_n_r = '1' else '0';
process (clk_vtu) is
begin
if rising_edge (clk_rf) then
t1_rst_rf_n_r <= cdc_rst_rf_n_r;
t2_rst_rf_n_r <= cdc_rst_rf_n_r;
if rising_edge (clk_vtu) then
t1_rst_rf_n_r <= cdc_rst_rf_n_h;
t1_rst_rf_n_h <= t1_rst_rf_n_r;
t2_rst_rf_n_r <= cdc_rst_rf_n_h;
t2_rst_rf_n_h <= t2_rst_rf_n_r;
t1_rst_vtu_pulse_r <= t1_rst_vtu_pulse;
t2_rst_vtu_pulse_r <= t2_rst_vtu_pulse;
end if;
end process;
t1_rst_vtu_pulse <= '1' when t1_rst_rf_n_h = '0' and t1_rst_rf_n_r = '1' else '0';
t2_rst_vtu_pulse <= '1' when t2_rst_rf_n_h = '0' and t2_rst_rf_n_r = '1' else '0';
-- Distribute to the region for logic (vtu). Note: divided by 8.
inst_rf_clkdiv_BUFR: BUFR
inst_rf_clkdiv8_BUFR: BUFR
generic map (
BUFR_DIVIDE => "8",
SIM_DEVICE => "7SERIES")
port map (
O => clk_vtu,
CE => '1', --cdc_rst_rf_n_r,
CLR => '0', --not cdc_rst_rf_n_r,
CE => '1',--cdc_rst_rf_n_h,
CLR => bufr_clr,
I => rf_clk_in );
inst_rf_clkdiv4_BUFR: BUFR
generic map (
BUFR_DIVIDE => "4",
SIM_DEVICE => "7SERIES")
port map (
O => clk_vtu_x2,
CE => '1',--cdc_rst_rf_n_r,
CLR => bufr_clr,
I => rf_clk_in );
inst_rf_clk_BUFR: BUFR
generic map (
--BUFR_DIVIDE => "1",
BUFR_DIVIDE => "1",
SIM_DEVICE => "7SERIES")
port map (
O => clk_rf,
CE => '1',--cdc_rst_rf_n_r,
CLR => '0',--not cdc_rst_rf_n_r,
CLR => bufr_clr,
I => rf_clk_in );
inst_rf_clk_special_BUFR: BUFR
generic map (
BUFR_DIVIDE => "1",
SIM_DEVICE => "7SERIES")
port map (
O => clk_rf_special,
CE => '1',--cdc_rst_rf_n_r,
CLR => '0',
I => rf_clk_in );
-- The RF sync signal into the trigger unit has a programmable delay
......@@ -242,7 +285,7 @@ begin
-- but the dynamic range is insufficient to cover our needs.
rf_activated <= '1' when rf_t1_sync_i = '1' else rf_activated_r;
rst_rf <= '1' when rf_t1_sync_i = '1' else
'0' when rst_rf_cnt_r = (unsigned(rf_t1_sync_cdelay_i) - 8) else rst_rf_r;
'0' when rst_rf_cnt_r = (unsigned(rf_t1_sync_cdelay_i) - unsigned(rf_rst_cdelay_offset_i)) else rst_rf_r;
rst_rf_cnt <= rst_rf_cnt_r + 1 when rst_rf = '1' and rf_activated = '1' else (others => '0');
-- Delay rf_t1_syncs such that we have stable RF at the trigger unit input after an nco_reset
......@@ -373,13 +416,15 @@ begin
port map (
clk_sys_i => clk_sys_i,
rst_sys_i => rst_sys_r,
rst_rf_n_i => t1_rst_rf_n_r,
rst_rf_n_i => t1_rst_rf_n_r,
rst_serdes_i => t1_rst_vtu_pulse_r,
wb_i => t1_wb_in,
wb_o => t1_wb_out,
clk_rf_io_i => rf_clk_io,
clk_rf_i => clk_rf,
clk_vtu_i => clk_vtu,
clk_vtu_x2_i => clk_vtu_x2,
sync_i => rf_sync_fb,
sync_x8_fb_i => X"00",
sync_x8_fb_o => rf_t1_sync_x8_fb,
......@@ -423,12 +468,14 @@ begin
clk_sys_i => clk_sys_i,
rst_sys_i => rst_sys_r,
rst_rf_n_i => t2_rst_rf_n_r,
rst_serdes_i => t2_rst_vtu_pulse_r,
wb_i => t2_wb_in,
wb_o => t2_wb_out,
clk_rf_io_i => rf_clk_io,
clk_rf_i => clk_rf,
clk_vtu_i => clk_vtu,
clk_vtu_x2_i => clk_vtu_x2,
sync_i => rf_t1_fb,
sync_x8_fb_i => rf_t1_sync_x8_fb,
sync_x8_fb_o => open,
......
hdl/rtl/x8oddr.vhd
View file @ 7ab6dc40
......@@ -113,7 +113,7 @@ begin
port map (
D1 => d1out_r,
D2 => d2out_r,
c => clk_rf_io_i,
c => clk_rf_i,
ce => '1',
q => ddr_data_o,
r => '0',
......
hdl/syn/wr2rf_vme/wr2rf_t1sync_falsepath.tcl
View file @ 7ab6dc40
......@@ -2,7 +2,11 @@
set_false_path -to [get_pins inst_rf1_trigger/rf_t1_i/g_t1_true.inst_ISERDESE2/D]
set_false_path -to [get_pins inst_rf2_trigger/rf_t1_i/g_t1_true.inst_ISERDESE2/D]
# This is a reset cleaned up circuit, from the nco_reset sourced in the WR clock domain
# This is a reset clean up circuit, from the nco_reset sourced in the WR clock domain
# destination path clocked with RF clock, source path clocked with WR (nco_reset)
set_false_path -to [get_pins inst_rf1_trigger/async_cdc_rst_rf_n_r_reg/CLR]
set_false_path -to [get_pins inst_rf1_trigger/cdc_rst_rf_n_r_reg/CLR]
set_false_path -to [get_pins inst_rf1_trigger/cdc_rst_rf_n_h_reg/CLR]
set_false_path -to [get_pins inst_rf2_trigger/async_cdc_rst_rf_n_r_reg/CLR]
set_false_path -to [get_pins inst_rf2_trigger/cdc_rst_rf_n_r_reg/CLR]
set_false_path -to [get_pins inst_rf2_trigger/cdc_rst_rf_n_h_reg/CLR]
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 7ab6dc40
This diff is collapsed.
software/libwr2rf/board.c
View file @ 7ab6dc40
......@@ -684,6 +684,16 @@ int libwr2rf_vtu_reset (struct libwr2rf_dev *dev, unsigned id, unsigned rst)
v &= ~TRIGUNIT_REGS_CONTROL_VTURESET;
libwr2rf_write16(dev, addr + TRIGUNIT_REGS_CONTROL, v);
if (rst) {
/* Also clear offline configuration in case of reset. */
v = libwr2rf_read16(dev, addr + TRIGUNIT_REGS_CONFIGOFFLINE);
if (v & TRIGUNIT_REGS_CONFIGOFFLINE_VALID)
{
v &= ~TRIGUNIT_REGS_CONFIGOFFLINE_VALID;
libwr2rf_write16(dev, addr + TRIGUNIT_REGS_CONFIGOFFLINE, v);
}
}
return 0;
}
......@@ -1151,3 +1161,36 @@ libwr2rf_configure_softstop_sel(struct libwr2rf_dev *dev, unsigned sel)
libwr2rf_write16(dev, addr, sel);
return 0;
}
void
libwr2rf_set_nco_reset_ignore (struct libwr2rf_dev *dev, unsigned ignore)
{
unsigned base_rf1 = WR2RF_VME_REGS_CTRL + WR2RF_CTRL_REGS_RF1_RFNCO;
unsigned base_rf2 = WR2RF_VME_REGS_CTRL + WR2RF_CTRL_REGS_RF2_RFNCO;
unsigned control_rf1;
unsigned control_rf2;
unsigned ncoctrl_addr = WR2RF_VME_REGS_CTRL + WR2RF_CTRL_REGS_NCO_RESET_CTRL;
unsigned ncoctrl;
control_rf1 = libwr2rf_16x32_read32(dev, base_rf1 + RFNCO_CONTROL);
control_rf2 = libwr2rf_16x32_read32(dev, base_rf2 + RFNCO_CONTROL);
ncoctrl = libwr2rf_read16(dev, ncoctrl_addr);
if (ignore) {
control_rf1 &= ~RFNCO_CONTROL_EXTRESETENABLE;
control_rf2 &= ~RFNCO_CONTROL_EXTRESETENABLE;
ncoctrl |= WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_DDS;
}
else {
control_rf1 |= RFNCO_CONTROL_EXTRESETENABLE;
control_rf2 |= RFNCO_CONTROL_EXTRESETENABLE;
ncoctrl &= ~WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_DDS;
}
libwr2rf_16x32_write32(dev, base_rf1 + RFNCO_CONTROL, control_rf1);
libwr2rf_16x32_write32(dev, base_rf2 + RFNCO_CONTROL, control_rf2);
libwr2rf_write16(dev, ncoctrl_addr, ncoctrl);
}
software/libwr2rf/libwr2rf/api.h
View file @ 7ab6dc40
......@@ -253,8 +253,10 @@ void libwr2rf_set_wrs_fixed_latency (struct libwr2rf_dev *dev,
unsigned libwr2rf_get_wrs_fixed_latency (struct libwr2rf_dev *dev);
/* Set WR streamer timeout latency: the maximum time the packet arrive in advance.
Too early coming packets are discarded. */
Too early coming packets are discarded. In WR cyckes ie 16ns. */
void libwr2rf_set_wrs_timeout_latency (struct libwr2rf_dev *dev, unsigned wr_cycles);
unsigned libwr2rf_get_wrs_timeout_latency (struct libwr2rf_dev *dev);
/* Ignore NCO reset from WR if IGNORE is set. */
void libwr2rf_set_nco_reset_ignore (struct libwr2rf_dev *dev, unsigned ignore);
#endif /* __LIBWR2RF__API__H_ */
software/libwr2rf/wr2rf.c
View file @ 7ab6dc40
......@@ -2584,11 +2584,56 @@ lemo_disp_dbg(struct libwr2rf_dev *dev, struct strb *strb, unsigned lemo)
val = libwr2rf_read16
(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_TMGIO1 + lemo*2);
strb_printf(strb, "out: ");
if (val == (1 << (LIBWR2RF_LEMO_DBG_WRS_SOFTSTOP - 1)))
if (val == (1 << (LIBWR2RF_LEMO_DBG_WRS_SOFTSTOP - 1))) {
unsigned vtu;
strb_printf(strb, "softstop");
else if (val == (1 << (LIBWR2RF_LEMO_DBG_WRS_SOFTSTART - 1)))
vtu = libwr2rf_read16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_SOFTSTART);
switch (vtu) {
case LIBWR2RF_RF1T1_SOFTSTOP_SEL:
strb_printf(strb, "(1.1)");
break;
case LIBWR2RF_RF1T2_SOFTSTOP_SEL:
strb_printf(strb, "(1.2)");
break;
case LIBWR2RF_RF2T1_SOFTSTOP_SEL:
strb_printf(strb, "(2.1)");
break;
case LIBWR2RF_RF2T2_SOFTSTOP_SEL:
strb_printf(strb, "(2.2)");
break;
default:
strb_printf(strb, "(bad)");
break;
}
}
else if (val == (1 << (LIBWR2RF_LEMO_DBG_WRS_SOFTSTART - 1))) {
unsigned vtu;
strb_printf(strb, "softstart");
else
vtu = libwr2rf_read16(dev, WR2RF_VME_REGS_INIT + WR2RF_INIT_REGS_SOFTSTART);
switch (vtu) {
case LIBWR2RF_RF1T1_SOFTSTART_SEL:
strb_printf(strb, "(1.1)");
break;
case LIBWR2RF_RF1T2_SOFTSTART_SEL:
strb_printf(strb, "(1.2)");
break;
case LIBWR2RF_RF2T1_SOFTSTART_SEL:
strb_printf(strb, "(2.1)");
break;
case LIBWR2RF_RF2T2_SOFTSTART_SEL:
strb_printf(strb, "(2.2)");
break;
default:
strb_printf(strb, "(bad)");
break;
}
} else
strb_printf(strb, "%s", xlat_get_name(dbg_reg, val, "??"));
}
......@@ -3738,6 +3783,21 @@ api_nco_reset_delay (struct libwr2rf_dev *dev, int argc, char **argv)
printf ("ERROR\n");
}
static void
api_nco_reset_ignore (struct libwr2rf_dev *dev, int argc, char **argv)
{
unsigned val;
if (argc != 2) {
printf ("usage: %s 0|1\n", argv[0]);
return;
}
val = strtoul(argv[1], NULL, 0);
libwr2rf_set_nco_reset_ignore(dev, val);
}
static void
api_dds_ioupdate_delay (struct libwr2rf_dev *dev, int argc, char **argv)
{
......@@ -3905,6 +3965,7 @@ static struct cmds cmds[] =
{ "api-nco-reset-delay", api_nco_reset_delay, "set nco reset delay"},
{ "api-tmgio", api_tmgio, "set lemo io output enable and termination"},
{ "api-tmgclk", api_tmgclk, "set lemo clk output enable and termination"},
{ "api-nco-reset-ignore", api_nco_reset_ignore, "ignore (or not) nco reset"},
{ "ftw-show", ftw_show, "show received ftw" },
{ "ftw-last", framerxtx_last, "display last ftw" },
{ "ftw-framerxtx", framerxtx_framerxtx, "display framerxtx registers" },
......
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