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wr2rf-vme
Commit 5f1be388 authored by John Gill's avatar John Gill
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Added module to generate 10 Mhz, synced by pps.

parent 006f6988
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Showing with 166 additions and 32 deletions
hdl/rtl/Manifest.py
View file @ 5f1be388
......@@ -13,7 +13,7 @@ files = ['vtu_blk.vhd',
'wr2rf_ocxo.vhd',
'wr2rf_lemo.vhd',
'wr2rf_dds.vhd',
'x8oddr.vhd',
'wr2rf_gen_10mhz.vhd',
'ila_syn.vhd'];
hdl/rtl/wr2rf_gen_10mhz.vhd 0 → 100644
View file @ 5f1be388
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
--
-- https://www.ohwr.org/projects/wr2rf-vme
--------------------------------------------------------------------------------
--
-- unit name: wr2rf_gen_10mhz
--
-- description: Provides a 10 MHz clock for front panel
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity wr2rf_gen_10mhz is
port (
clk125m_i : in std_logic;
rst_clk125m_i : in std_logic;
clk500m_i : in std_logic;
rst_clk500m_i : in std_logic;
pps_i : in std_logic;
pps_valid_i : in std_logic;
clk10m_o : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of wr2rf_gen_10mhz : entity is "yes";
end entity;
architecture rtl of wr2rf_gen_10mhz is
constant d4width : integer := 4;
subtype d4_t is std_logic_vector(d4width-1 downto 0);
type v4_t is array (natural range <>) of d4_t;
signal pat_rom : v4_t(24 downto 0) := (X"0",
X"0", X"0", X"0", X"0", X"0", X"7",
X"f", X"f", X"f", X"f", X"f", X"c",
X"0", X"0", X"0", X"0", X"0", X"1",
X"f", X"f", X"f", X"f", X"f", X"f");
signal idx : unsigned(4 downto 0);
signal idx_r : unsigned(4 downto 0);
signal pat_syncd : std_logic;
signal pat_syncd_r : std_logic;
signal pattern : std_logic_vector(3 downto 0);
signal pattern_r : std_logic_vector(3 downto 0);
signal clk10m : std_logic;
begin
pat_syncd <= '0' when pps_valid_i = '0' else
'1' when pps_valid_i = '1' and pps_i = '1' else pat_syncd_r;
idx <= (others => '0') when pat_syncd = '0' or idx_r = 24 else idx_r + 1;
pattern <= (others => '0') when pat_syncd = '0' else pat_rom(to_integer(idx_r));
process (clk125m_i) is
begin
if rising_edge(clk125m_i) then
if rst_clk125m_i = '1' then
pat_syncd_r <= '0';
idx_r <= (others => '0');
pattern_r <= (others => '0');
else
pat_syncd_r <= pat_syncd;
idx_r <= idx;
pattern_r <= pattern;
end if;
end if;
end process;
inst_10mhz_oserdes : OSERDESE2
generic map (
DATA_RATE_OQ => "SDR", -- DDR, SDR
DATA_RATE_TQ => "SDR", -- DDR, BUF, SDR
DATA_WIDTH => 4, -- Parallel data width (2-8,10,14)
INIT_OQ => '0', -- Initial value of OQ output (1'b0,1'b1)
INIT_TQ => '0', -- Initial value of TQ output (1'b0,1'b1)
SERDES_MODE => "MASTER", -- MASTER, SLAVE
SRVAL_OQ => '0', -- OQ output value when SR is used (1'b0,1'b1)
SRVAL_TQ => '0', -- TQ output value when SR is used (1'b0,1'b1)
TBYTE_CTL => "FALSE", -- Enable tristate byte operation (FALSE, TRUE)
TBYTE_SRC => "FALSE", -- Tristate byte source (FALSE, TRUE)
TRISTATE_WIDTH => 1 ) -- 3-state converter width (1,4)
port map (
OFB => open, -- 1-bit output: Feedback path for data
OQ => clk10m_o, -- 1-bit output: Data path output
SHIFTOUT1 => open, -- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT2 => open,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => clk500m_i, -- 1-bit input: High speed clock
CLKDIV => clk125m_i, -- 1-bit input: Divided clock
D1 => pattern_r(0), -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D2 => pattern_r(1),
D3 => pattern_r(2),
D4 => pattern_r(3),
D5 => '0',
D6 => '0',
D7 => '0',
D8 => '0',
OCE => '1', -- 1-bit input: Output data clock enable
RST => rst_clk125m_i, -- 1-bit input: Reset
SHIFTIN1 => '0', -- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN2 => '0',
T1 => '0', -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' ); -- 1-bit input: 3-state clock enable
end architecture;
hdl/rtl/wr2rf_regs_core.vhd
View file @ 5f1be388
......@@ -338,8 +338,8 @@ begin
init_hwinfo_ident_jtagRemoteDisable_i => '1',
init_hwinfo_ident_extendedID_i => "0000000",
init_hwinfo_ident_cardID_i => x"56",
init_hwinfo_firmwareVersion_i => x"0000_11_00",
init_hwinfo_memMapVersion_i => x"0000_11_00",
init_hwinfo_firmwareVersion_i => x"0000_12_00",
init_hwinfo_memMapVersion_i => x"0000_12_00",
init_hwinfo_echo_echo_o => open,
init_fw_update_i => wb_fw_update_in,
......
hdl/rtl/wr2rf_sysclks.vhd
View file @ 5f1be388
......@@ -43,9 +43,6 @@ entity wr2rf_sysclks is
rst_clk62m5_n_o : out std_logic;
rst_clk62m5_o : out std_logic;
-- For ext_clk, shifted to be resynchronized.
clk10m_o : out std_logic;
clk125m_o : out std_logic;
rst_clk125m_n_o : out std_logic;
rst_clk125m_o : out std_logic;
......@@ -81,7 +78,7 @@ architecture rtl of wr2rf_sysclks is
signal clkout3 : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4 : std_logic;
signal clkout5 : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
......@@ -130,11 +127,11 @@ begin
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_DIVIDE => 100, -- 10 MHz
CLKOUT4_PHASE => -135.000,
CLKOUT4_DIVIDE => 2, -- 500 MHz
CLKOUT4_PHASE => 0.000,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_USE_FINE_PS => True,
CLKOUT5_DIVIDE => 2, -- 500 MHz
CLKOUT4_USE_FINE_PS => FALSE,
CLKOUT5_DIVIDE => 0,
CLKOUT5_PHASE => 0.000,
CLKOUT5_DUTY_CYCLE => 0.500,
CLKOUT5_USE_FINE_PS => FALSE,
......@@ -151,7 +148,7 @@ begin
CLKOUT3 => clkout3,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4,
CLKOUT5 => clkout5,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
......@@ -200,10 +197,6 @@ begin
O => clkfbout_buf );
clks(0) <= clkout0; -- this is clock buffered later by a bufgmux
-- clk62m5_buf : BUFG
-- port map (
-- I => clkout0,
-- O => clks(0) );
clk125m_buf : BUFG
port map (
......@@ -221,14 +214,9 @@ begin
O => clks(3) );
clk500m_buf : BUFG
port map (
I => clkout5,
O => clks(4) );
clk10m_buf : BUFG
port map (
I => clkout4,
O => clk10m_o );
O => clks(4) );
mmcm_locked_o <= locked;
......@@ -259,6 +247,6 @@ begin
rst_clk125m_o <= not rsts_n(1);
rst_clk250m_o <= not rsts_n(2);
rst_clk200m_o <= not rsts_n(3);
rst_clk500m_o <= not rsts_n(4);
rst_clk500m_o <= not rsts_n(4);
end architecture;
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 5f1be388
......@@ -113,10 +113,6 @@ entity wr2rf_vme is
ext_10m_dir_o : out std_logic;
ext_pps_dir_o : out std_logic;
-- 62.5 MHz external reference clock (the above * 6.25)
-- clk_ext_62m5_p_i : in std_logic;
-- clk_ext_62m5_n_i : in std_logic;
-- SFP 1
sfp1_tx_n_o : out std_logic;
sfp1_tx_p_o : out std_logic;
......@@ -503,6 +499,7 @@ architecture rtl of wr2rf_vme is
signal rf2_t2_stop_sel : std_logic_vector(6 downto 1);
signal pps : std_logic;
signal pps_r : std_logic;
signal tm_link_up : std_logic;
signal tm_time_valid : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
......@@ -668,8 +665,12 @@ architecture rtl of wr2rf_vme is
attribute keep_hierarchy of inst_vme_core : label is "yes";
attribute keep_hierarchy of inst_RFFrameTransceiver : label is "yes";
attribute keep_hierarchy of inst_xwr_streamers : label is "yes";
--attribute keep_hierarchy of inst_WR_CORE : label is "yes";
attribute IOB : string;
attribute keep : string;
attribute IOB of pps_r : signal is "true";
attribute keep of pps_r : signal is "true";
begin
-- Poweron reset.
......@@ -738,8 +739,6 @@ begin
rst_clk62m5_n_o => rst_clk62m5_n,
rst_clk62m5_o => rst_clk62m5,
clk10m_o => clk_ext_10m_o,
clk125m_o => clk125m,
rst_clk125m_n_o => rst_clk125m_n,
rst_clk125m_o => rst_clk125m,
......@@ -756,6 +755,16 @@ begin
rst_clk200m_n_o => rst_clk200m_n,
rst_clk200m_o => rst_clk200m );
wr2rf_gen_10mhz_i : entity work.wr2rf_gen_10mhz
port map (
clk125m_i => clk125m,
rst_clk125m_i => rst_clk125m,
clk500m_i => clk500m,
rst_clk500m_i => rst_clk500m,
pps_i => pps_p,
pps_valid_i => tm_time_valid,
clk10m_o => clk_ext_10m_o );
------------------------------------------------------------------------------
-- Dedicated clock for GTP
------------------------------------------------------------------------------
......@@ -1194,9 +1203,10 @@ begin
process(clk_sys_62m5) is
begin
if rising_edge(clk_sys_62m5) then
pps_o <= pps_p;
pps_r <= pps_p;
end if;
end process;
pps_o <= pps_r;
-----------------------------------------------------------------------------
-- VME64x Core and buffers
......@@ -1700,7 +1710,10 @@ begin
ila_sigs(78 downto 64) <= rf1_tu_ila_dbg(14 downto 0);
ila_sigs(79) <= rf1_nco_reset_cdelayed;
ila_sigs(95 downto 80) <= rf2_tu_ila_dbg(15 downto 0);
ila_sigs(99 downto 96) <= (others => '0');
ila_sigs(96) <= '0';
ila_sigs(97) <= '0';
ila_sigs(98) <= pps_p;
ila_sigs(99) <= '0';
--ila_sigs(69 downto 64) <= rf1_t1_start_sel;
--ila_sigs(70) <= rf1_t1_start;
--ila_sigs(71) <= rf1_t2_start;
......
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