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wr2rf-vme
Commit 54e6328b authored by John Gill's avatar John Gill
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Merging serdes_rst fix into Master

parents ac04e3e3 d360b4dd
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Showing with 224 additions and 166 deletions
hdl/rtl/vtu_blk.vhd
View file @ 54e6328b
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hdl/rtl/wr2rf_regs_core.vhd
View file @ 54e6328b
......@@ -338,8 +338,8 @@ begin
init_hwinfo_ident_jtagRemoteDisable_i => '1',
init_hwinfo_ident_extendedID_i => "0000000",
init_hwinfo_ident_cardID_i => x"56",
init_hwinfo_firmwareVersion_i => x"0000_10_00",
init_hwinfo_memMapVersion_i => x"0000_10_00",
init_hwinfo_firmwareVersion_i => x"0000_11_00",
init_hwinfo_memMapVersion_i => x"0000_11_00",
init_hwinfo_echo_echo_o => open,
init_fw_update_i => wb_fw_update_in,
......
hdl/rtl/wr2rf_rftrigger.vhd
View file @ 54e6328b
......@@ -166,6 +166,15 @@ architecture rtl of wr2rf_rftrigger is
signal rf_sync_fb : std_logic;
signal rf_t1_sync_x8_fb : std_logic_vector(7 downto 0);
signal bufr_clr : std_logic;
signal clk_rf_special : std_logic;
signal t1_rst_rf_n_h : std_logic;
signal t2_rst_rf_n_h : std_logic;
signal t1_rst_vtu_pulse : std_logic;
signal t2_rst_vtu_pulse : std_logic;
signal t1_rst_vtu_pulse_r : std_logic;
signal t2_rst_vtu_pulse_r : std_logic;
attribute async_reg : string;
attribute async_reg of async_cdc_rst_rf_n_r : signal is "true";
......@@ -198,26 +207,35 @@ begin
I => rf_clk_in );
-- Sync nco_reset into the RF clk domain
process (rf_clk_in, rst_rf_r) is
process (clk_rf_special, rst_rf_r) is
begin
if rst_rf_r = '1' then
async_cdc_rst_rf_n_r <= '0';
cdc_rst_rf_n_r <= '0';
cdc_rst_rf_n_h <= '0';
elsif rising_edge (rf_clk_in) then
elsif rising_edge (clk_rf_special) then
async_cdc_rst_rf_n_r <= '1';
cdc_rst_rf_n_r <= async_cdc_rst_rf_n_r;
cdc_rst_rf_n_h <= cdc_rst_rf_n_r;
end if;
end process;
process (clk_rf) is
bufr_clr <= '1' when cdc_rst_rf_n_h = '0' and cdc_rst_rf_n_r = '1' else '0';
process (clk_vtu) is
begin
if rising_edge (clk_rf) then
if rising_edge (clk_vtu) then
t1_rst_rf_n_r <= cdc_rst_rf_n_h;
t2_rst_rf_n_r <= cdc_rst_rf_n_h;
t1_rst_rf_n_h <= t1_rst_rf_n_r;
t2_rst_rf_n_r <= cdc_rst_rf_n_h;
t2_rst_rf_n_h <= t2_rst_rf_n_r;
t1_rst_vtu_pulse_r <= t1_rst_vtu_pulse;
t2_rst_vtu_pulse_r <= t2_rst_vtu_pulse;
end if;
end process;
t1_rst_vtu_pulse <= '1' when t1_rst_rf_n_h = '0' and t1_rst_rf_n_r = '1' else '0';
t2_rst_vtu_pulse <= '1' when t2_rst_rf_n_h = '0' and t2_rst_rf_n_r = '1' else '0';
-- Distribute to the region for logic (vtu). Note: divided by 8.
inst_rf_clkdiv8_BUFR: BUFR
......@@ -227,7 +245,7 @@ begin
port map (
O => clk_vtu,
CE => '1',--cdc_rst_rf_n_h,
CLR => '0',--not cdc_rst_rf_n_r,
CLR => bufr_clr,
I => rf_clk_in );
inst_rf_clkdiv4_BUFR: BUFR
......@@ -237,8 +255,8 @@ begin
port map (
O => clk_vtu_x2,
CE => '1',--cdc_rst_rf_n_r,
CLR => '0',--not cdc_rst_rf_n_r,
I => rf_clk_in );
CLR => bufr_clr,
I => rf_clk_in );
inst_rf_clk_BUFR: BUFR
generic map (
......@@ -247,7 +265,17 @@ begin
port map (
O => clk_rf,
CE => '1',--cdc_rst_rf_n_r,
CLR => '0',--not cdc_rst_rf_n_r,
CLR => bufr_clr,
I => rf_clk_in );
inst_rf_clk_special_BUFR: BUFR
generic map (
BUFR_DIVIDE => "1",
SIM_DEVICE => "7SERIES")
port map (
O => clk_rf_special,
CE => '1',--cdc_rst_rf_n_r,
CLR => '0',
I => rf_clk_in );
-- The RF sync signal into the trigger unit has a programmable delay
......@@ -388,7 +416,8 @@ begin
port map (
clk_sys_i => clk_sys_i,
rst_sys_i => rst_sys_r,
rst_rf_n_i => t1_rst_rf_n_r,
rst_rf_n_i => t1_rst_rf_n_r,
rst_serdes_i => t1_rst_vtu_pulse_r,
wb_i => t1_wb_in,
wb_o => t1_wb_out,
......@@ -439,6 +468,7 @@ begin
clk_sys_i => clk_sys_i,
rst_sys_i => rst_sys_r,
rst_rf_n_i => t2_rst_rf_n_r,
rst_serdes_i => t2_rst_vtu_pulse_r,
wb_i => t2_wb_in,
wb_o => t2_wb_out,
......
hdl/rtl/x8oddr.vhd
View file @ 54e6328b
......@@ -113,7 +113,7 @@ begin
port map (
D1 => d1out_r,
D2 => d2out_r,
c => clk_rf_io_i,
c => clk_rf_i,
ce => '1',
q => ddr_data_o,
r => '0',
......
hdl/syn/wr2rf_vme/wr2rf_vme.tcl
View file @ 54e6328b
#set projDir [file dirname [info script]]
#
#set_param general.maxThreads 8
#get_param general.maxThreads
#
## Xilinx speed grades: 1,2,3: 1 = slowest, 3 = fastest
#set speed 2
#set kintex7 xc7k160tfbg676-${speed}
#set device ${kintex7}
#
#set top wr2rf_vme
#
## Check hdlmake has generated file dependencies
#if {![file exists files.tcl]} {
# puts "File: files.tcl not found, please check hdlmake has generated the file dependencies."
# exit 1
#}
#
#source files.tcl
#
## constraint files
#set swap_sfp false
#if {$swap_sfp eq "true"} {
# read_xdc $projDir/${top}_sfp_swap.xdc
#} else {
# read_xdc $projDir/${top}_sfp.xdc
#}
#read_xdc $projDir/${top}.xdc
#
#set start_time [clock seconds]
#
##synth_design -rtl -top ${top} -part ${device} > ${top}_synth.log
#synth_design -top ${top} -part ${device} > ${top}_synth.log
#write_checkpoint -force ${top}_synth
#
#source wr2rf_async_regs.tcl
#source wr2rf_maxdelays.tcl
#source wr2rf_dmtd_falsepath.tcl
#source wr2rf_t1sync_falsepath.tcl
set projDir [file dirname [info script]]
set_param general.maxThreads 8
get_param general.maxThreads
# Xilinx speed grades: 1,2,3: 1 = slowest, 3 = fastest
set speed 2
set kintex7 xc7k160tfbg676-${speed}
set device ${kintex7}
set top wr2rf_vme
# Check hdlmake has generated file dependencies
if {![file exists files.tcl]} {
puts "File: files.tcl not found, please check hdlmake has generated the file dependencies."
exit 1
}
source files.tcl
# constraint files
set swap_sfp false
if {$swap_sfp eq "true"} {
read_xdc $projDir/${top}_sfp_swap.xdc
} else {
read_xdc $projDir/${top}_sfp.xdc
}
read_xdc $projDir/${top}.xdc
set start_time [clock seconds]
#synth_design -rtl -top ${top} -part ${device} > ${top}_synth.log
synth_design -top ${top} -part ${device} > ${top}_synth.log
write_checkpoint -force ${top}_synth
source wr2rf_async_regs.tcl
source wr2rf_maxdelays.tcl
source wr2rf_dmtd_falsepath.tcl
source wr2rf_t1sync_falsepath.tcl
#opt_design -directive Explore -verbose > ${top}_opt.log
#write_checkpoint -force ${top}_opt
......
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 54e6328b
......@@ -43,8 +43,8 @@ entity wr2rf_vme is
generic (
g_simulation : integer := 0;
g_dpram_size : integer := 131072/4;
-- g_dpram_initf : string := "../../../../dependencies/wrpc-sw/wrc-wr2rf-enabled-snmp-and-auxdiags.bram";
g_dpram_initf : string := "";
g_dpram_initf : string := "../../../../dependencies/wrpc-sw/wrc-wr2rf-enabled-snmp-and-auxdiags.bram";
-- g_dpram_initf : string := "";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -1697,24 +1697,27 @@ begin
ila_sigs(15) <= wb_wrc_out.ack;
ila_sigs(63 downto 16) <= vme_dbg;
--ila_sigs(79 downto 64) <= rf1_tu_ila_dbg(15 downto 0);
ila_sigs(69 downto 64) <= rf1_t1_start_sel;
ila_sigs(70) <= rf1_t1_start;
ila_sigs(71) <= rf1_t2_start;
ila_sigs(77 downto 72) <= rf1_t1_stop_sel;
ila_sigs(78) <= rf1_t1_stop;
ila_sigs(79) <= rf1_t2_stop;
ila_sigs(80) <= iodelay_reset;
ila_sigs(81) <= rf1_t1_rst;
ila_sigs(82) <= rf1_t2_rst;
ila_sigs(83) <= rf2_t1_rst;
ila_sigs(84) <= rf2_t2_rst;
ila_sigs(85) <= reconfigure;
ila_sigs(86) <= rf1_t1_delay_latch;
ila_sigs(87) <= rf1_t2_delay_latch;
ila_sigs(88) <= rf2_t1_delay_latch;
ila_sigs(89) <= rf2_t2_delay_latch;
ila_sigs(99 downto 90) <= rf_trig_ff_delay;
ila_sigs(78 downto 64) <= rf1_tu_ila_dbg(14 downto 0);
ila_sigs(79) <= rf1_nco_reset_cdelayed;
ila_sigs(95 downto 80) <= rf2_tu_ila_dbg(15 downto 0);
ila_sigs(99 downto 96) <= (others => '0');
--ila_sigs(69 downto 64) <= rf1_t1_start_sel;
--ila_sigs(70) <= rf1_t1_start;
--ila_sigs(71) <= rf1_t2_start;
--ila_sigs(77 downto 72) <= rf1_t1_stop_sel;
--ila_sigs(78) <= rf1_t1_stop;
--ila_sigs(79) <= rf1_t2_stop;
--ila_sigs(80) <= iodelay_reset;
--ila_sigs(81) <= rf1_t1_rst;
--ila_sigs(82) <= rf1_t2_rst;
--ila_sigs(83) <= rf2_t1_rst;
--ila_sigs(84) <= rf2_t2_rst;
--ila_sigs(85) <= reconfigure;
--ila_sigs(86) <= rf1_t1_delay_latch;
--ila_sigs(87) <= rf1_t2_delay_latch;
--ila_sigs(88) <= rf2_t1_delay_latch;
--ila_sigs(89) <= rf2_t2_delay_latch;
--ila_sigs(99 downto 90) <= rf_trig_ff_delay;
ila_sigs(100) <= clk_ext_rst;
ila_sigs(101) <= clk_ext_stopped;
ila_sigs(102) <= clk_ext_mul_locked;
......
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