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wr2rf-vme
Commits
45543e63
Commit
45543e63
authored
Jun 05, 2023
by
Tristan Gingold
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Add one aux channel (connected to tmg clk1)
parent
a48b1797
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10 additions
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3 deletions
+10
-3
wr2rf_vme.vhd
hdl/top/wr2rf_vme/wr2rf_vme.vhd
+10
-3
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hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @
45543e63
...
...
@@ -45,7 +45,7 @@ entity wr2rf_vme is
g_simulation
:
integer
:
=
0
;
g_dpram_size
:
integer
:
=
131072
/
4
;
g_dpram_initf
:
string
:
=
"../../../../dependencies/wrpc-sw-file/wrc.bram"
;
g_dpram_initf
:
string
:
=
""
;
--
g_dpram_initf : string := "";
g_diag_id
:
integer
:
=
0
;
g_diag_ver
:
integer
:
=
0
;
g_diag_ro_size
:
integer
:
=
0
;
...
...
@@ -336,6 +336,8 @@ architecture rtl of wr2rf_vme is
signal
rst_clk500m_n
:
std_logic
;
signal
rst_clk500m
:
std_logic
;
signal
clk_aux_in
:
std_logic
;
-- Wishbone bus from master
signal
wb_vme_out
:
t_wishbone_master_out
;
signal
wb_vme_in
:
t_wishbone_master_in
;
...
...
@@ -800,6 +802,10 @@ begin
pps_valid_i
=>
tm_time_valid
,
clk10m_o
=>
clk_ext_10m_o
);
-- Input for dtmd (to check quality of clocks).
-- This is hard-coded to tmg clk 1
clk_aux_in
<=
tmg_clk_i
(
1
);
------------------------------------------------------------------------------
-- Dedicated clock for GTP
------------------------------------------------------------------------------
...
...
@@ -871,7 +877,8 @@ begin
--g_ram_address_space_size_kb => 256,
g_phys_uart
=>
true
,
-- Is false OK ?
g_virtual_uart
=>
true
,
g_aux_clks
=>
0
,
g_vuart_fifo_size
=>
1024
,
g_aux_clks
=>
1
,
g_ep_rxbuf_size
=>
1024
,
g_tx_runt_padding
=>
true
,
g_records_for_phy
=>
true
,
...
...
@@ -883,7 +890,6 @@ begin
g_aux_sdb
=>
c_wrc_periph3_sdb
,
g_softpll_enable_debugger
=>
true
,
g_softpll_use_sampled_ref_clocks
=>
true
,
g_vuart_fifo_size
=>
1024
,
g_diag_id
=>
c_diag_id
,
g_diag_ver
=>
c_diag_ver
,
g_diag_ro_size
=>
c_diag_ro_size
,
...
...
@@ -892,6 +898,7 @@ begin
clk_sys_i
=>
clk_sys_62m5
,
clk_dmtd_i
=>
clk_dmtd_62m5
,
clk_ref_i
=>
clk_sys_62m5
,
--clk_125m_ref,
clk_aux_i
(
0
)
=>
clk_aux_in
,
clk_ext_i
=>
clk_ext_10m
,
clk_ext_mul_i
=>
clk_ext_mul
,
clk_ext_stopped_i
=>
clk_ext_stopped
,
...
...
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